Commit 50d1eefa authored by Georgi Djakov's avatar Georgi Djakov
Browse files

Merge branch 'icc-sc7280' into icc-next 

Add Epoch Subsystem (EPSS) L3 provider support on SM7280 SoCs.

* icc-sc7280
  dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280
  interconnect: qcom: Add EPSS L3 support on SC7280

Link: https://lore.kernel.org/r/1634812857-10676-1-git-send-email-okukatla@codeaurora.org


Signed-off-by: default avatarGeorgi Djakov <djakov@kernel.org>
parents 1f41bada 6a61d1d1

Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml

+1 −0
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ properties: 
  compatible:

    enum:

      - qcom,sc7180-osm-l3

      - qcom,sc7280-epss-l3

      - qcom,sc8180x-osm-l3

      - qcom,sdm845-osm-l3

      - qcom,sm8150-osm-l3

drivers/interconnect/qcom/osm-l3.c

+19 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.

 */



#include <linux/bitfield.h>
@@ -15,6 +15,7 @@ 
#include <dt-bindings/interconnect/qcom,osm-l3.h>



#include "sc7180.h"

#include "sc7280.h"

#include "sc8180x.h"

#include "sdm845.h"

#include "sm8150.h"
@@ -114,6 +115,22 @@ static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = { 
	.reg_perf_state = OSM_REG_PERF_STATE,

};



DEFINE_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, SC7280_SLAVE_EPSS_L3);

DEFINE_QNODE(sc7280_epss_l3, SC7280_SLAVE_EPSS_L3, 32);



static const struct qcom_osm_l3_node *sc7280_epss_l3_nodes[] = {

	[MASTER_EPSS_L3_APPS] = &sc7280_epss_apps_l3,

	[SLAVE_EPSS_L3_SHARED] = &sc7280_epss_l3,

};



static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = {

	.nodes = sc7280_epss_l3_nodes,

	.num_nodes = ARRAY_SIZE(sc7280_epss_l3_nodes),

	.lut_row_size = EPSS_LUT_ROW_SIZE,

	.reg_freq_lut = EPSS_REG_FREQ_LUT,

	.reg_perf_state = EPSS_REG_PERF_STATE,

};



DEFINE_QNODE(sc8180x_osm_apps_l3, SC8180X_MASTER_OSM_L3_APPS, 32, SC8180X_SLAVE_OSM_L3);

DEFINE_QNODE(sc8180x_osm_l3, SC8180X_SLAVE_OSM_L3, 32);
@@ -326,6 +343,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev) 


static const struct of_device_id osm_l3_of_match[] = {

	{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },

	{ .compatible = "qcom,sc7280-epss-l3", .data = &sc7280_icc_epss_l3 },

	{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },

	{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },

	{ .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 },

drivers/interconnect/qcom/sc7280.h

+2 −0
Original line number Diff line number Diff line
@@ -150,5 +150,7 @@ 
#define SC7280_SLAVE_PCIE_1			139

#define SC7280_SLAVE_QDSS_STM			140

#define SC7280_SLAVE_TCU			141

#define SC7280_MASTER_EPSS_L3_APPS		142

#define SC7280_SLAVE_EPSS_L3			143



#endif