Commit 50c4a644 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/fifo/nv50-: rip out dma channels 



I honestly don't even know why...  These have never been used.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
Reviewed-by: default avatarLyude Paul <lyude@redhat.com>
parent e78b1b54

drivers/gpu/drm/nouveau/include/nvif/class.h

+0 −2
Original line number Diff line number Diff line
@@ -61,8 +61,6 @@ 
#define NV10_CHANNEL_DMA                              /* cl506b.h */ 0x0000006e

#define NV17_CHANNEL_DMA                              /* cl506b.h */ 0x0000176e

#define NV40_CHANNEL_DMA                              /* cl506b.h */ 0x0000406e

#define NV50_CHANNEL_DMA                              /* cl506e.h */ 0x0000506e

#define G82_CHANNEL_DMA                               /* cl826e.h */ 0x0000826e



#define NV50_CHANNEL_GPFIFO                           /* cl506f.h */ 0x0000506f

#define G82_CHANNEL_GPFIFO                            /* cl826f.h */ 0x0000826f

drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild

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Original line number Diff line number Diff line
@@ -27,8 +27,6 @@ nvkm-y += nvkm/engine/fifo/dmanv04.o 
nvkm-y += nvkm/engine/fifo/dmanv10.o

nvkm-y += nvkm/engine/fifo/dmanv17.o

nvkm-y += nvkm/engine/fifo/dmanv40.o

nvkm-y += nvkm/engine/fifo/dmanv50.o

nvkm-y += nvkm/engine/fifo/dmag84.o



nvkm-y += nvkm/engine/fifo/gpfifonv50.o

nvkm-y += nvkm/engine/fifo/gpfifog84.o

drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h

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Original line number Diff line number Diff line
@@ -48,8 +48,6 @@ void nv50_fifo_chan_object_dtor(struct nvkm_fifo_chan *, int); 
int g84_fifo_chan_ctor(struct nv50_fifo *, u64 vmm, u64 push,

		       const struct nvkm_oclass *, struct nv50_fifo_chan *);



extern const struct nvkm_fifo_chan_oclass nv50_fifo_dma_oclass;

extern const struct nvkm_fifo_chan_oclass nv50_fifo_gpfifo_oclass;

extern const struct nvkm_fifo_chan_oclass g84_fifo_dma_oclass;

extern const struct nvkm_fifo_chan_oclass g84_fifo_gpfifo_oclass;

#endif

drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c

deleted100644 → 0
+0 −94
Original line number Diff line number Diff line 
/*

 * Copyright 2012 Red Hat Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Ben Skeggs

 */

#include "channv50.h"



#include <core/client.h>

#include <core/ramht.h>



#include <nvif/class.h>

#include <nvif/cl826e.h>

#include <nvif/unpack.h>



static int

g84_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,

		 void *data, u32 size, struct nvkm_object **pobject)

{

	struct nvkm_object *parent = oclass->parent;

	union {

		struct g82_channel_dma_v0 v0;

	} *args = data;

	struct nv50_fifo *fifo = nv50_fifo(base);

	struct nv50_fifo_chan *chan;

	int ret = -ENOSYS;



	nvif_ioctl(parent, "create channel dma size %d\n", size);

	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {

		nvif_ioctl(parent, "create channel dma vers %d vmm %llx "

				   "pushbuf %llx offset %016llx\n",

			   args->v0.version, args->v0.vmm, args->v0.pushbuf,

			   args->v0.offset);

		if (!args->v0.pushbuf)

			return -EINVAL;

	} else

		return ret;



	if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))

		return -ENOMEM;

	*pobject = &chan->base.object;



	ret = g84_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf,

				 oclass, chan);

	if (ret)

		return ret;



	args->v0.chid = chan->base.chid;



	nvkm_kmap(chan->ramfc);

	nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset));

	nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset));

	nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset));

	nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset));

	nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078);

	nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);

	nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4);

	nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff);

	nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff);

	nvkm_wo32(chan->ramfc, 0x78, 0x00000000);

	nvkm_wo32(chan->ramfc, 0x7c, 0x30000001);

	nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |

				     (4 << 24) /* SEARCH_FULL */ |

				     (chan->ramht->gpuobj->node->offset >> 4));

	nvkm_wo32(chan->ramfc, 0x88, chan->cache->addr >> 10);

	nvkm_wo32(chan->ramfc, 0x98, chan->base.inst->addr >> 12);

	nvkm_done(chan->ramfc);

	return 0;

}



const struct nvkm_fifo_chan_oclass

g84_fifo_dma_oclass = {

	.base.oclass = G82_CHANNEL_DMA,

	.base.minver = 0,

	.base.maxver = 0,

	.ctor = g84_fifo_dma_new,

};

drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c

deleted100644 → 0
+0 −92
Original line number Diff line number Diff line 
/*

 * Copyright 2012 Red Hat Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: Ben Skeggs

 */

#include "channv50.h"



#include <core/client.h>

#include <core/ramht.h>



#include <nvif/class.h>

#include <nvif/cl506e.h>

#include <nvif/unpack.h>



static int

nv50_fifo_dma_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,

		  void *data, u32 size, struct nvkm_object **pobject)

{

	struct nvkm_object *parent = oclass->parent;

	union {

		struct nv50_channel_dma_v0 v0;

	} *args = data;

	struct nv50_fifo *fifo = nv50_fifo(base);

	struct nv50_fifo_chan *chan;

	int ret = -ENOSYS;



	nvif_ioctl(parent, "create channel dma size %d\n", size);

	if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {

		nvif_ioctl(parent, "create channel dma vers %d vmm %llx "

				   "pushbuf %llx offset %016llx\n",

			   args->v0.version, args->v0.vmm, args->v0.pushbuf,

			   args->v0.offset);

		if (!args->v0.pushbuf)

			return -EINVAL;

	} else

		return ret;



	if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))

		return -ENOMEM;

	*pobject = &chan->base.object;



	ret = nv50_fifo_chan_ctor(fifo, args->v0.vmm, args->v0.pushbuf,

				  oclass, chan);

	if (ret)

		return ret;



	args->v0.chid = chan->base.chid;



	nvkm_kmap(chan->ramfc);

	nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset));

	nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset));

	nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset));

	nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset));

	nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078);

	nvkm_wo32(chan->ramfc, 0x44, 0x01003fff);

	nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4);

	nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff);

	nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff);

	nvkm_wo32(chan->ramfc, 0x78, 0x00000000);

	nvkm_wo32(chan->ramfc, 0x7c, 0x30000001);

	nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) |

				     (4 << 24) /* SEARCH_FULL */ |

				     (chan->ramht->gpuobj->node->offset >> 4));

	nvkm_done(chan->ramfc);

	return 0;

}



const struct nvkm_fifo_chan_oclass

nv50_fifo_dma_oclass = {

	.base.oclass = NV50_CHANNEL_DMA,

	.base.minver = 0,

	.base.maxver = 0,

	.ctor = nv50_fifo_dma_new,

};