Commit 50a12d8f authored by José Roberto de Souza's avatar José Roberto de Souza
Browse files

drm/i915: Do not enable PSR in the next modeset after a error 



When we detect a error and disable PSR, it is kept disabled until the
next modeset but as the sink already show signs that it do not
properly work with PSR lets disabled it for good to avoid any
additional flickering.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181121225441.18785-3-jose.souza@intel.com
parent 2f8e7ea9

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -504,6 +504,7 @@ struct i915_psr { 
	u8 sink_sync_latency;

	ktime_t last_entry_attempt;

	ktime_t last_exit;

	bool sink_not_reliable;

};



enum intel_pch {

drivers/gpu/drm/i915/intel_psr.c

+9 −1
Original line number Diff line number Diff line
@@ -527,6 +527,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, 
		return;

	}



	if (dev_priv->psr.sink_not_reliable) {

		DRM_DEBUG_KMS("PSR sink implementation is not reliable\n");

		return;

	}



	if (IS_HASWELL(dev_priv) &&

	    I915_READ(HSW_STEREO_3D_CTL(crtc_state->cpu_transcoder)) &

		      S3D_ENABLE) {
@@ -1123,6 +1128,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp) 
	if ((val & DP_PSR_SINK_STATE_MASK) == DP_PSR_SINK_INTERNAL_ERROR) {

		DRM_DEBUG_KMS("PSR sink internal error, disabling PSR\n");

		intel_psr_disable_locked(intel_dp);

		psr->sink_not_reliable = true;

	}



	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_ERROR_STATUS, &val) != 1) {
@@ -1140,8 +1146,10 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp) 
	if (val & ~errors)

		DRM_ERROR("PSR_ERROR_STATUS unhandled errors %x\n",

			  val & ~errors);

	if (val & errors)

	if (val & errors) {

		intel_psr_disable_locked(intel_dp);

		psr->sink_not_reliable = true;

	}

	/* clear status register */

	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS, val);

exit: