Commit 5099600b authored by zhangshuowen96's avatar zhangshuowen96
Browse files

drivers: misc: sdma-dae: support interrupt init and handle 

kunpeng inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I9W355


CVE: NA

----------------------------------------------------------------------

Add init functions of sdma interrupt and add handle functions
of ioe interrupt.

Signed-off-by: default avatarzhangshuowen96 <zhangshuowen@hisilicon.com>
parent 7d91f398

drivers/misc/sdma-dae/sdma_hal.h

+5 −1
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
#include "sdma_reg.h"



#define RW_R_R			0644

#define SDMA_IRQ_NUM_MAX	512



#define sdma_wmb() (asm volatile("dsb st" ::: "memory"))
@@ -50,7 +51,6 @@ struct hisi_sdma_channel { 
 * @base_addr: SDMA I/O base phyisical address

 * @name: SDMA device name in the /dev directory

 */



struct hisi_sdma_device {

	u16 idx;

	u16 node_idx;
@@ -72,6 +72,10 @@ struct hisi_sdma_device { 
	resource_size_t base_addr_size;

	u64 common_base_addr;

	resource_size_t common_base_addr_size;



	int irq_cnt;

	int base_vir_irq;

	int irq[SDMA_IRQ_NUM_MAX];

};



struct hisi_sdma_core_device {

drivers/misc/sdma-dae/sdma_irq.c

0 → 100644
+106 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-or-later

#include <linux/interrupt.h>

#include <linux/io.h>

#include <linux/platform_device.h>

#include "sdma_irq.h"



#define HISI_SDMA_IRQ_FUNC_NAME(n)	"SDMA_CHANNEL##n_IOE_IRQ"

#define SDMA_IOE_NUM_MAX		(SDMA_IRQ_NUM_MAX / 2)

#define SDMA_IOC_NUM_MAX		SDMA_IOE_NUM_MAX

#define SDMA_IOC_MASKED_STATUS		0x1

#define SDMA_IOC_IOE_MASKED_STATUS	0x3



static spinlock_t err_set_lock[SDMA_IOE_NUM_MAX];



irqreturn_t sdma_chn_ioe_irq_handle(int irq, void *psdma_dev)

{

	struct hisi_sdma_device *sdma;

	u32 err_status;

	u32 cqe_status;

	u32 cqe_sqeid;

	int chn;



	sdma = (struct hisi_sdma_device *)psdma_dev;

	chn = irq - sdma->base_vir_irq - SDMA_IOC_NUM_MAX - HISI_STARS_CHN_NUM;

	if (chn < 0 || chn >= SDMA_IOC_NUM_MAX) {

		dev_err(&sdma->pdev->dev, "SDMA IOE int%d wrong!\n", irq);

		return 0;

	}



	spin_lock(&err_set_lock[chn]);

	err_status = sdma_channel_get_err_status(&sdma->channels[chn]);

	cqe_status = sdma_channel_get_cqe_status(&sdma->channels[chn]);

	cqe_sqeid = sdma_channel_get_cqe_sqeid(&sdma->channels[chn]);



	sdma->channels[chn].sync_info_base->ioe.ch_err_status = err_status;

	sdma->channels[chn].sync_info_base->ioe.ch_cqe_status = cqe_status;

	sdma->channels[chn].sync_info_base->ioe.ch_cqe_sqeid = cqe_sqeid;



	sdma_channel_clear_ioe_status(sdma->io_base + chn * HISI_SDMA_CHANNEL_IOMEM_SIZE);

	sdma_channel_clear_cqe_status(sdma->io_base + chn * HISI_SDMA_CHANNEL_IOMEM_SIZE);

	spin_unlock(&err_set_lock[chn]);



	dev_info(&sdma->pdev->dev, "sdma chn%d error status = %u, ioe clear\n", chn, err_status);



	return 0;

}



void sdma_irq_init(struct hisi_sdma_device *sdma)

{

	struct platform_device *pdev;

	void __iomem *io_addr;

	int ret, vir_irq;

	u32 irq_cnt;

	u32 i;



	pdev = sdma->pdev;

	for (i = 0; i < sdma->nr_channel + HISI_STARS_CHN_NUM; i++) {

		io_addr = sdma->io_orig_base + i * HISI_SDMA_CHANNEL_IOMEM_SIZE;

		sdma_channel_set_irq_mask(io_addr, SDMA_IOC_MASKED_STATUS);

	}



	sdma_int_converge_dis(sdma->common_base);



	irq_cnt = (u32)sdma->irq_cnt;

	for (i = 0; i < irq_cnt; i++) {

		vir_irq = platform_get_irq(pdev, i);

		if (vir_irq < 0) {

			dev_err(&pdev->dev, "get vir_irq[idx:%d] failed:%d!\n", i, vir_irq);

			sdma->irq[i] = -1;

			continue;

		}

		sdma->irq[i] = vir_irq;

		if (i == 0) {

			sdma->base_vir_irq = vir_irq;

			dev_info(&pdev->dev, "base_vir_irq = %d\n", vir_irq);

		}

	}



	for (i = INT_CH_IOE_SDMAM_0 + HISI_STARS_CHN_NUM; i <= INT_CH_IOE_SDMAM_255; i++) {

		if (sdma->irq[i] == -1)

			continue;



		ret = devm_request_irq(&sdma->pdev->dev, sdma->irq[i], sdma_chn_ioe_irq_handle,

				       IRQF_ONESHOT, HISI_SDMA_IRQ_FUNC_NAME(i), sdma);

		if (ret != 0) {

			dev_err(&pdev->dev, "request_irq failed, ret=%d", ret);

			continue;

		}

	}



	for (i = 0; i < SDMA_IOE_NUM_MAX; i++)

		spin_lock_init(&err_set_lock[i]);

}



void sdma_irq_deinit(struct hisi_sdma_device *sdma)

{

	struct platform_device *pdev;

	void __iomem *io_addr;

	u32 i;



	pdev = sdma->pdev;

	for (i = 0; i < sdma->nr_channel + HISI_STARS_CHN_NUM; i++) {

		io_addr = sdma->io_orig_base + i * HISI_SDMA_CHANNEL_IOMEM_SIZE;

		sdma_channel_set_irq_mask(io_addr, SDMA_IOC_IOE_MASKED_STATUS);

	}

}

drivers/misc/sdma-dae/sdma_irq.h

0 → 100644
+145 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-or-later */

#ifndef __HISI_SDMA_IRQ_H__

#define __HISI_SDMA_IRQ_H__



#include "sdma_hal.h"



#define SDMA_IRQ_NAME_LENGTH_MAX	256

#define MBIX_IOREMAP_SIZE_WORD		4



enum sdma_irq_type {

	INT_CH_IOC_SDMAM_0, INT_CH_IOC_SDMAM_1, INT_CH_IOC_SDMAM_2, INT_CH_IOC_SDMAM_3,

	INT_CH_IOC_SDMAM_4, INT_CH_IOC_SDMAM_5, INT_CH_IOC_SDMAM_6, INT_CH_IOC_SDMAM_7,

	INT_CH_IOC_SDMAM_8, INT_CH_IOC_SDMAM_9, INT_CH_IOC_SDMAM_10, INT_CH_IOC_SDMAM_11,

	INT_CH_IOC_SDMAM_12, INT_CH_IOC_SDMAM_13, INT_CH_IOC_SDMAM_14, INT_CH_IOC_SDMAM_15,

	INT_CH_IOC_SDMAM_16, INT_CH_IOC_SDMAM_17, INT_CH_IOC_SDMAM_18, INT_CH_IOC_SDMAM_19,

	INT_CH_IOC_SDMAM_20, INT_CH_IOC_SDMAM_21, INT_CH_IOC_SDMAM_22, INT_CH_IOC_SDMAM_23,

	INT_CH_IOC_SDMAM_24, INT_CH_IOC_SDMAM_25, INT_CH_IOC_SDMAM_26, INT_CH_IOC_SDMAM_27,

	INT_CH_IOC_SDMAM_28, INT_CH_IOC_SDMAM_29, INT_CH_IOC_SDMAM_30, INT_CH_IOC_SDMAM_31,

	INT_CH_IOC_SDMAM_32, INT_CH_IOC_SDMAM_33, INT_CH_IOC_SDMAM_34, INT_CH_IOC_SDMAM_35,

	INT_CH_IOC_SDMAM_36, INT_CH_IOC_SDMAM_37, INT_CH_IOC_SDMAM_38, INT_CH_IOC_SDMAM_39,

	INT_CH_IOC_SDMAM_40, INT_CH_IOC_SDMAM_41, INT_CH_IOC_SDMAM_42, INT_CH_IOC_SDMAM_43,

	INT_CH_IOC_SDMAM_44, INT_CH_IOC_SDMAM_45, INT_CH_IOC_SDMAM_46, INT_CH_IOC_SDMAM_47,

	INT_CH_IOC_SDMAM_48, INT_CH_IOC_SDMAM_49, INT_CH_IOC_SDMAM_50, INT_CH_IOC_SDMAM_51,

	INT_CH_IOC_SDMAM_52, INT_CH_IOC_SDMAM_53, INT_CH_IOC_SDMAM_54, INT_CH_IOC_SDMAM_55,

	INT_CH_IOC_SDMAM_56, INT_CH_IOC_SDMAM_57, INT_CH_IOC_SDMAM_58, INT_CH_IOC_SDMAM_59,

	INT_CH_IOC_SDMAM_60, INT_CH_IOC_SDMAM_61, INT_CH_IOC_SDMAM_62, INT_CH_IOC_SDMAM_63,

	INT_CH_IOC_SDMAM_64, INT_CH_IOC_SDMAM_65, INT_CH_IOC_SDMAM_66, INT_CH_IOC_SDMAM_67,

	INT_CH_IOC_SDMAM_68, INT_CH_IOC_SDMAM_69, INT_CH_IOC_SDMAM_70, INT_CH_IOC_SDMAM_71,

	INT_CH_IOC_SDMAM_72, INT_CH_IOC_SDMAM_73, INT_CH_IOC_SDMAM_74, INT_CH_IOC_SDMAM_75,

	INT_CH_IOC_SDMAM_76, INT_CH_IOC_SDMAM_77, INT_CH_IOC_SDMAM_78, INT_CH_IOC_SDMAM_79,

	INT_CH_IOC_SDMAM_80, INT_CH_IOC_SDMAM_81, INT_CH_IOC_SDMAM_82, INT_CH_IOC_SDMAM_83,

	INT_CH_IOC_SDMAM_84, INT_CH_IOC_SDMAM_85, INT_CH_IOC_SDMAM_86, INT_CH_IOC_SDMAM_87,

	INT_CH_IOC_SDMAM_88, INT_CH_IOC_SDMAM_89, INT_CH_IOC_SDMAM_90, INT_CH_IOC_SDMAM_91,

	INT_CH_IOC_SDMAM_92, INT_CH_IOC_SDMAM_93, INT_CH_IOC_SDMAM_94, INT_CH_IOC_SDMAM_95,

	INT_CH_IOC_SDMAM_96, INT_CH_IOC_SDMAM_97, INT_CH_IOC_SDMAM_98, INT_CH_IOC_SDMAM_99,

	INT_CH_IOC_SDMAM_100, INT_CH_IOC_SDMAM_101, INT_CH_IOC_SDMAM_102, INT_CH_IOC_SDMAM_103,

	INT_CH_IOC_SDMAM_104, INT_CH_IOC_SDMAM_105, INT_CH_IOC_SDMAM_106, INT_CH_IOC_SDMAM_107,

	INT_CH_IOC_SDMAM_108, INT_CH_IOC_SDMAM_109, INT_CH_IOC_SDMAM_110, INT_CH_IOC_SDMAM_111,

	INT_CH_IOC_SDMAM_112, INT_CH_IOC_SDMAM_113, INT_CH_IOC_SDMAM_114, INT_CH_IOC_SDMAM_115,

	INT_CH_IOC_SDMAM_116, INT_CH_IOC_SDMAM_117, INT_CH_IOC_SDMAM_118, INT_CH_IOC_SDMAM_119,

	INT_CH_IOC_SDMAM_120, INT_CH_IOC_SDMAM_121, INT_CH_IOC_SDMAM_122, INT_CH_IOC_SDMAM_123,

	INT_CH_IOC_SDMAM_124, INT_CH_IOC_SDMAM_125, INT_CH_IOC_SDMAM_126, INT_CH_IOC_SDMAM_127,

	INT_CH_IOC_SDMAM_128, INT_CH_IOC_SDMAM_129, INT_CH_IOC_SDMAM_130, INT_CH_IOC_SDMAM_131,

	INT_CH_IOC_SDMAM_132, INT_CH_IOC_SDMAM_133, INT_CH_IOC_SDMAM_134, INT_CH_IOC_SDMAM_135,

	INT_CH_IOC_SDMAM_136, INT_CH_IOC_SDMAM_137, INT_CH_IOC_SDMAM_138, INT_CH_IOC_SDMAM_139,

	INT_CH_IOC_SDMAM_140, INT_CH_IOC_SDMAM_141, INT_CH_IOC_SDMAM_142, INT_CH_IOC_SDMAM_143,

	INT_CH_IOC_SDMAM_144, INT_CH_IOC_SDMAM_145, INT_CH_IOC_SDMAM_146, INT_CH_IOC_SDMAM_147,

	INT_CH_IOC_SDMAM_148, INT_CH_IOC_SDMAM_149, INT_CH_IOC_SDMAM_150, INT_CH_IOC_SDMAM_151,

	INT_CH_IOC_SDMAM_152, INT_CH_IOC_SDMAM_153, INT_CH_IOC_SDMAM_154, INT_CH_IOC_SDMAM_155,

	INT_CH_IOC_SDMAM_156, INT_CH_IOC_SDMAM_157, INT_CH_IOC_SDMAM_158, INT_CH_IOC_SDMAM_159,

	INT_CH_IOC_SDMAM_160, INT_CH_IOC_SDMAM_161, INT_CH_IOC_SDMAM_162, INT_CH_IOC_SDMAM_163,

	INT_CH_IOC_SDMAM_164, INT_CH_IOC_SDMAM_165, INT_CH_IOC_SDMAM_166, INT_CH_IOC_SDMAM_167,

	INT_CH_IOC_SDMAM_168, INT_CH_IOC_SDMAM_169, INT_CH_IOC_SDMAM_170, INT_CH_IOC_SDMAM_171,

	INT_CH_IOC_SDMAM_172, INT_CH_IOC_SDMAM_173, INT_CH_IOC_SDMAM_174, INT_CH_IOC_SDMAM_175,

	INT_CH_IOC_SDMAM_176, INT_CH_IOC_SDMAM_177, INT_CH_IOC_SDMAM_178, INT_CH_IOC_SDMAM_179,

	INT_CH_IOC_SDMAM_180, INT_CH_IOC_SDMAM_181, INT_CH_IOC_SDMAM_182, INT_CH_IOC_SDMAM_183,

	INT_CH_IOC_SDMAM_184, INT_CH_IOC_SDMAM_185, INT_CH_IOC_SDMAM_186, INT_CH_IOC_SDMAM_187,

	INT_CH_IOC_SDMAM_188, INT_CH_IOC_SDMAM_189, INT_CH_IOC_SDMAM_190, INT_CH_IOC_SDMAM_191,

	INT_CH_IOC_SDMAM_192, INT_CH_IOC_SDMAM_193, INT_CH_IOC_SDMAM_194, INT_CH_IOC_SDMAM_195,

	INT_CH_IOC_SDMAM_196, INT_CH_IOC_SDMAM_197, INT_CH_IOC_SDMAM_198, INT_CH_IOC_SDMAM_199,

	INT_CH_IOC_SDMAM_200, INT_CH_IOC_SDMAM_201, INT_CH_IOC_SDMAM_202, INT_CH_IOC_SDMAM_203,

	INT_CH_IOC_SDMAM_204, INT_CH_IOC_SDMAM_205, INT_CH_IOC_SDMAM_206, INT_CH_IOC_SDMAM_207,

	INT_CH_IOC_SDMAM_208, INT_CH_IOC_SDMAM_209, INT_CH_IOC_SDMAM_210, INT_CH_IOC_SDMAM_211,

	INT_CH_IOC_SDMAM_212, INT_CH_IOC_SDMAM_213, INT_CH_IOC_SDMAM_214, INT_CH_IOC_SDMAM_215,

	INT_CH_IOC_SDMAM_216, INT_CH_IOC_SDMAM_217, INT_CH_IOC_SDMAM_218, INT_CH_IOC_SDMAM_219,

	INT_CH_IOC_SDMAM_220, INT_CH_IOC_SDMAM_221, INT_CH_IOC_SDMAM_222, INT_CH_IOC_SDMAM_223,

	INT_CH_IOC_SDMAM_224, INT_CH_IOC_SDMAM_225, INT_CH_IOC_SDMAM_226, INT_CH_IOC_SDMAM_227,

	INT_CH_IOC_SDMAM_228, INT_CH_IOC_SDMAM_229, INT_CH_IOC_SDMAM_230, INT_CH_IOC_SDMAM_231,

	INT_CH_IOC_SDMAM_232, INT_CH_IOC_SDMAM_233, INT_CH_IOC_SDMAM_234, INT_CH_IOC_SDMAM_235,

	INT_CH_IOC_SDMAM_236, INT_CH_IOC_SDMAM_237, INT_CH_IOC_SDMAM_238, INT_CH_IOC_SDMAM_239,

	INT_CH_IOC_SDMAM_240, INT_CH_IOC_SDMAM_241, INT_CH_IOC_SDMAM_242, INT_CH_IOC_SDMAM_243,

	INT_CH_IOC_SDMAM_244, INT_CH_IOC_SDMAM_245, INT_CH_IOC_SDMAM_246, INT_CH_IOC_SDMAM_247,

	INT_CH_IOC_SDMAM_248, INT_CH_IOC_SDMAM_249, INT_CH_IOC_SDMAM_250, INT_CH_IOC_SDMAM_251,

	INT_CH_IOC_SDMAM_252, INT_CH_IOC_SDMAM_253, INT_CH_IOC_SDMAM_254, INT_CH_IOC_SDMAM_255,



	INT_CH_IOE_SDMAM_0, INT_CH_IOE_SDMAM_1, INT_CH_IOE_SDMAM_2, INT_CH_IOE_SDMAM_3,

	INT_CH_IOE_SDMAM_4, INT_CH_IOE_SDMAM_5, INT_CH_IOE_SDMAM_6, INT_CH_IOE_SDMAM_7,

	INT_CH_IOE_SDMAM_8, INT_CH_IOE_SDMAM_9, INT_CH_IOE_SDMAM_10, INT_CH_IOE_SDMAM_11,

	INT_CH_IOE_SDMAM_12, INT_CH_IOE_SDMAM_13, INT_CH_IOE_SDMAM_14, INT_CH_IOE_SDMAM_15,

	INT_CH_IOE_SDMAM_16, INT_CH_IOE_SDMAM_17, INT_CH_IOE_SDMAM_18, INT_CH_IOE_SDMAM_19,

	INT_CH_IOE_SDMAM_20, INT_CH_IOE_SDMAM_21, INT_CH_IOE_SDMAM_22, INT_CH_IOE_SDMAM_23,

	INT_CH_IOE_SDMAM_24, INT_CH_IOE_SDMAM_25, INT_CH_IOE_SDMAM_26, INT_CH_IOE_SDMAM_27,

	INT_CH_IOE_SDMAM_28, INT_CH_IOE_SDMAM_29, INT_CH_IOE_SDMAM_30, INT_CH_IOE_SDMAM_31,

	INT_CH_IOE_SDMAM_32, INT_CH_IOE_SDMAM_33, INT_CH_IOE_SDMAM_34, INT_CH_IOE_SDMAM_35,

	INT_CH_IOE_SDMAM_36, INT_CH_IOE_SDMAM_37, INT_CH_IOE_SDMAM_38, INT_CH_IOE_SDMAM_39,

	INT_CH_IOE_SDMAM_40, INT_CH_IOE_SDMAM_41, INT_CH_IOE_SDMAM_42, INT_CH_IOE_SDMAM_43,

	INT_CH_IOE_SDMAM_44, INT_CH_IOE_SDMAM_45, INT_CH_IOE_SDMAM_46, INT_CH_IOE_SDMAM_47,

	INT_CH_IOE_SDMAM_48, INT_CH_IOE_SDMAM_49, INT_CH_IOE_SDMAM_50, INT_CH_IOE_SDMAM_51,

	INT_CH_IOE_SDMAM_52, INT_CH_IOE_SDMAM_53, INT_CH_IOE_SDMAM_54, INT_CH_IOE_SDMAM_55,

	INT_CH_IOE_SDMAM_56, INT_CH_IOE_SDMAM_57, INT_CH_IOE_SDMAM_58, INT_CH_IOE_SDMAM_59,

	INT_CH_IOE_SDMAM_60, INT_CH_IOE_SDMAM_61, INT_CH_IOE_SDMAM_62, INT_CH_IOE_SDMAM_63,

	INT_CH_IOE_SDMAM_64, INT_CH_IOE_SDMAM_65, INT_CH_IOE_SDMAM_66, INT_CH_IOE_SDMAM_67,

	INT_CH_IOE_SDMAM_68, INT_CH_IOE_SDMAM_69, INT_CH_IOE_SDMAM_70, INT_CH_IOE_SDMAM_71,

	INT_CH_IOE_SDMAM_72, INT_CH_IOE_SDMAM_73, INT_CH_IOE_SDMAM_74, INT_CH_IOE_SDMAM_75,

	INT_CH_IOE_SDMAM_76, INT_CH_IOE_SDMAM_77, INT_CH_IOE_SDMAM_78, INT_CH_IOE_SDMAM_79,

	INT_CH_IOE_SDMAM_80, INT_CH_IOE_SDMAM_81, INT_CH_IOE_SDMAM_82, INT_CH_IOE_SDMAM_83,

	INT_CH_IOE_SDMAM_84, INT_CH_IOE_SDMAM_85, INT_CH_IOE_SDMAM_86, INT_CH_IOE_SDMAM_87,

	INT_CH_IOE_SDMAM_88, INT_CH_IOE_SDMAM_89, INT_CH_IOE_SDMAM_90, INT_CH_IOE_SDMAM_91,

	INT_CH_IOE_SDMAM_92, INT_CH_IOE_SDMAM_93, INT_CH_IOE_SDMAM_94, INT_CH_IOE_SDMAM_95,

	INT_CH_IOE_SDMAM_96, INT_CH_IOE_SDMAM_97, INT_CH_IOE_SDMAM_98, INT_CH_IOE_SDMAM_99,

	INT_CH_IOE_SDMAM_100, INT_CH_IOE_SDMAM_101, INT_CH_IOE_SDMAM_102, INT_CH_IOE_SDMAM_103,

	INT_CH_IOE_SDMAM_104, INT_CH_IOE_SDMAM_105, INT_CH_IOE_SDMAM_106, INT_CH_IOE_SDMAM_107,

	INT_CH_IOE_SDMAM_108, INT_CH_IOE_SDMAM_109, INT_CH_IOE_SDMAM_110, INT_CH_IOE_SDMAM_111,

	INT_CH_IOE_SDMAM_112, INT_CH_IOE_SDMAM_113, INT_CH_IOE_SDMAM_114, INT_CH_IOE_SDMAM_115,

	INT_CH_IOE_SDMAM_116, INT_CH_IOE_SDMAM_117, INT_CH_IOE_SDMAM_118, INT_CH_IOE_SDMAM_119,

	INT_CH_IOE_SDMAM_120, INT_CH_IOE_SDMAM_121, INT_CH_IOE_SDMAM_122, INT_CH_IOE_SDMAM_123,

	INT_CH_IOE_SDMAM_124, INT_CH_IOE_SDMAM_125, INT_CH_IOE_SDMAM_126, INT_CH_IOE_SDMAM_127,

	INT_CH_IOE_SDMAM_128, INT_CH_IOE_SDMAM_129, INT_CH_IOE_SDMAM_130, INT_CH_IOE_SDMAM_131,

	INT_CH_IOE_SDMAM_132, INT_CH_IOE_SDMAM_133, INT_CH_IOE_SDMAM_134, INT_CH_IOE_SDMAM_135,

	INT_CH_IOE_SDMAM_136, INT_CH_IOE_SDMAM_137, INT_CH_IOE_SDMAM_138, INT_CH_IOE_SDMAM_139,

	INT_CH_IOE_SDMAM_140, INT_CH_IOE_SDMAM_141, INT_CH_IOE_SDMAM_142, INT_CH_IOE_SDMAM_143,

	INT_CH_IOE_SDMAM_144, INT_CH_IOE_SDMAM_145, INT_CH_IOE_SDMAM_146, INT_CH_IOE_SDMAM_147,

	INT_CH_IOE_SDMAM_148, INT_CH_IOE_SDMAM_149, INT_CH_IOE_SDMAM_150, INT_CH_IOE_SDMAM_151,

	INT_CH_IOE_SDMAM_152, INT_CH_IOE_SDMAM_153, INT_CH_IOE_SDMAM_154, INT_CH_IOE_SDMAM_155,

	INT_CH_IOE_SDMAM_156, INT_CH_IOE_SDMAM_157, INT_CH_IOE_SDMAM_158, INT_CH_IOE_SDMAM_159,

	INT_CH_IOE_SDMAM_160, INT_CH_IOE_SDMAM_161, INT_CH_IOE_SDMAM_162, INT_CH_IOE_SDMAM_163,

	INT_CH_IOE_SDMAM_164, INT_CH_IOE_SDMAM_165, INT_CH_IOE_SDMAM_166, INT_CH_IOE_SDMAM_167,

	INT_CH_IOE_SDMAM_168, INT_CH_IOE_SDMAM_169, INT_CH_IOE_SDMAM_170, INT_CH_IOE_SDMAM_171,

	INT_CH_IOE_SDMAM_172, INT_CH_IOE_SDMAM_173, INT_CH_IOE_SDMAM_174, INT_CH_IOE_SDMAM_175,

	INT_CH_IOE_SDMAM_176, INT_CH_IOE_SDMAM_177, INT_CH_IOE_SDMAM_178, INT_CH_IOE_SDMAM_179,

	INT_CH_IOE_SDMAM_180, INT_CH_IOE_SDMAM_181, INT_CH_IOE_SDMAM_182, INT_CH_IOE_SDMAM_183,

	INT_CH_IOE_SDMAM_184, INT_CH_IOE_SDMAM_185, INT_CH_IOE_SDMAM_186, INT_CH_IOE_SDMAM_187,

	INT_CH_IOE_SDMAM_188, INT_CH_IOE_SDMAM_189, INT_CH_IOE_SDMAM_190, INT_CH_IOE_SDMAM_191,

	INT_CH_IOE_SDMAM_192, INT_CH_IOE_SDMAM_193, INT_CH_IOE_SDMAM_194, INT_CH_IOE_SDMAM_195,

	INT_CH_IOE_SDMAM_196, INT_CH_IOE_SDMAM_197, INT_CH_IOE_SDMAM_198, INT_CH_IOE_SDMAM_199,

	INT_CH_IOE_SDMAM_200, INT_CH_IOE_SDMAM_201, INT_CH_IOE_SDMAM_202, INT_CH_IOE_SDMAM_203,

	INT_CH_IOE_SDMAM_204, INT_CH_IOE_SDMAM_205, INT_CH_IOE_SDMAM_206, INT_CH_IOE_SDMAM_207,

	INT_CH_IOE_SDMAM_208, INT_CH_IOE_SDMAM_209, INT_CH_IOE_SDMAM_210, INT_CH_IOE_SDMAM_211,

	INT_CH_IOE_SDMAM_212, INT_CH_IOE_SDMAM_213, INT_CH_IOE_SDMAM_214, INT_CH_IOE_SDMAM_215,

	INT_CH_IOE_SDMAM_216, INT_CH_IOE_SDMAM_217, INT_CH_IOE_SDMAM_218, INT_CH_IOE_SDMAM_219,

	INT_CH_IOE_SDMAM_220, INT_CH_IOE_SDMAM_221, INT_CH_IOE_SDMAM_222, INT_CH_IOE_SDMAM_223,

	INT_CH_IOE_SDMAM_224, INT_CH_IOE_SDMAM_225, INT_CH_IOE_SDMAM_226, INT_CH_IOE_SDMAM_227,

	INT_CH_IOE_SDMAM_228, INT_CH_IOE_SDMAM_229, INT_CH_IOE_SDMAM_230, INT_CH_IOE_SDMAM_231,

	INT_CH_IOE_SDMAM_232, INT_CH_IOE_SDMAM_233, INT_CH_IOE_SDMAM_234, INT_CH_IOE_SDMAM_235,

	INT_CH_IOE_SDMAM_236, INT_CH_IOE_SDMAM_237, INT_CH_IOE_SDMAM_238, INT_CH_IOE_SDMAM_239,

	INT_CH_IOE_SDMAM_240, INT_CH_IOE_SDMAM_241, INT_CH_IOE_SDMAM_242, INT_CH_IOE_SDMAM_243,

	INT_CH_IOE_SDMAM_244, INT_CH_IOE_SDMAM_245, INT_CH_IOE_SDMAM_246, INT_CH_IOE_SDMAM_247,

	INT_CH_IOE_SDMAM_248, INT_CH_IOE_SDMAM_249, INT_CH_IOE_SDMAM_250, INT_CH_IOE_SDMAM_251,

	INT_CH_IOE_SDMAM_252, INT_CH_IOE_SDMAM_253, INT_CH_IOE_SDMAM_254, INT_CH_IOE_SDMAM_255,

};



void sdma_irq_init(struct hisi_sdma_device *sdma);

void sdma_irq_deinit(struct hisi_sdma_device *sdma);



#endif

drivers/misc/sdma-dae/sdma_main.c

+13 −0
Original line number Diff line number Diff line
@@ -9,6 +9,8 @@ 
#include <linux/device.h>



#include "sdma_hal.h"

#include "sdma_irq.h"

#include "sdma_auth.h"



#define UPPER_SHIFT		32

#define MAX_INPUT_LENGTH	128
@@ -259,6 +261,13 @@ static int of_sdma_collect_info(struct platform_device *pdev, struct hisi_sdma_d 
	psdma_dev->common_base_addr = res->start;

	psdma_dev->common_base_addr_size = resource_size(res);



	psdma_dev->irq_cnt = platform_irq_count(pdev);

	if (psdma_dev->irq_cnt < 0) {

		dev_err(&pdev->dev, "Get irq_cnt failed!\n");

		return psdma_dev->irq_cnt;

	}

	dev_info(&pdev->dev, "get irq_cnt:%d\n", psdma_dev->irq_cnt);



	return 0;

}
@@ -302,6 +311,8 @@ static int sdma_init_device_info(struct hisi_sdma_device *psdma_dev) 
		return ret;

	}



	sdma_irq_init(psdma_dev);



	return 0;

}
@@ -374,6 +385,7 @@ static int sdma_device_probe(struct platform_device *pdev) 
	iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA);

	iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF);

deinit_device:

	sdma_irq_deinit(psdma_dev);

	sdma_destroy_channels(psdma_dev);

	iounmap(psdma_dev->common_base);

	iounmap(psdma_dev->io_orig_base);
@@ -391,6 +403,7 @@ static int sdma_device_remove(struct platform_device *pdev) 
	device_destroy(sdma_class, MKDEV(hisi_sdma_core_device.sdma_major, psdma_dev->idx));

	cdev_del(&psdma_dev->cdev);



	sdma_irq_deinit(psdma_dev);

	sdma_destroy_channels(psdma_dev);

	iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA);

	iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_IOPF);