Commit 5089c4a8 authored by Aurabindo Pillai's avatar Aurabindo Pillai Committed by Alex Deucher
Browse files

drm/amd/display: ignore modifiers when checking for format support 



[Why&How]
There are cases where swizzle modes are set but modifiers arent. For
such a userspace, we need not check modifiers while checking
compatibilty in the drm hook for checking plane format.

Ignore checking modifiers but check the DCN generation for the
supported swizzle mode.

v2: squash in unused variable removal (Alex)

Signed-off-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: default avatarMarek Olšák <marek.olsak@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f2a50025

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+46 −7
Original line number Diff line number Diff line
@@ -4936,8 +4936,7 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane, 
{

	struct amdgpu_device *adev = drm_to_adev(plane->dev);

	const struct drm_format_info *info = drm_format_info(format);

	int i;



	struct hw_asic_id asic_id = adev->dm.dc->ctx->asic_id;

	enum dm_micro_swizzle microtile = modifier_gfx9_swizzle_mode(modifier) & 3;



	if (!info)
@@ -4953,13 +4952,53 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane, 
		return true;

	}



	/* Check that the modifier is on the list of the plane's supported modifiers. */

	for (i = 0; i < plane->modifier_count; i++) {

		if (modifier == plane->modifiers[i])

	/* check if swizzle mode is supported by this version of DCN */

	switch (asic_id.chip_family) {

		case FAMILY_SI:

		case FAMILY_CI:

		case FAMILY_KV:

		case FAMILY_CZ:

		case FAMILY_VI:

			/* asics before AI does not have modifier support */

			return false;

			break;

		case FAMILY_AI:

		case FAMILY_RV:

		case FAMILY_NV:

		case FAMILY_VGH:

		case FAMILY_YELLOW_CARP:

		case AMDGPU_FAMILY_GC_10_3_6:

		case AMDGPU_FAMILY_GC_10_3_7:

			switch (AMD_FMT_MOD_GET(TILE, modifier)) {

				case AMD_FMT_MOD_TILE_GFX9_64K_R_X:

				case AMD_FMT_MOD_TILE_GFX9_64K_D_X:

				case AMD_FMT_MOD_TILE_GFX9_64K_S_X:

				case AMD_FMT_MOD_TILE_GFX9_64K_D:

					return true;

					break;

				default:

					return false;

					break;

			}

	if (i == plane->modifier_count)

			break;

		case AMDGPU_FAMILY_GC_11_0_0:

			switch (AMD_FMT_MOD_GET(TILE, modifier)) {

				case AMD_FMT_MOD_TILE_GFX11_256K_R_X:

				case AMD_FMT_MOD_TILE_GFX9_64K_R_X:

				case AMD_FMT_MOD_TILE_GFX9_64K_D_X:

				case AMD_FMT_MOD_TILE_GFX9_64K_S_X:

				case AMD_FMT_MOD_TILE_GFX9_64K_D:

					return true;

					break;

				default:

					return false;

					break;

			}

			break;

		default:

			ASSERT(0); /* Unknown asic */

			break;

	}



	/*

	 * For D swizzle the canonical modifier depends on the bpp, so check