Commit 507156f5 authored by Sivaprakash Murugesan's avatar Sivaprakash Murugesan Committed by Vinod Koul
Browse files

phy: qcom-qmp: Add USB QMP PHY support for IPQ8074 



Add QMP USB PHY found in IPQ8074

Co-developed-by: default avatarBalaji Prakash J <bjagadee@codeaurora.org>
Signed-off-by: default avatarBalaji Prakash J <bjagadee@codeaurora.org>
Signed-off-by: default avatarSivaprakash Murugesan <sivaprak@codeaurora.org>
Tested-by: default avatarSricharan R <sricharan@codeaurora.org>
Reviewed-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1591625479-4483-4-git-send-email-sivaprak@codeaurora.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent ba971c2f

drivers/phy/qualcomm/phy-qcom-qmp.c

+102 −0
Original line number Diff line number Diff line
@@ -198,6 +198,81 @@ static const unsigned int sm8150_ufsphy_regs_layout[QPHY_LAYOUT_SIZE] = { 
	[QPHY_SW_RESET]			= QPHY_V4_PCS_UFS_SW_RESET,

};



static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),

	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),

	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),

	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),

	QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),

	QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),

	/* PLL and Loop filter settings */

	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),

	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),

	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),

	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),

	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),

	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),

	/* SSC settings */

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),

	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),

};



static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),

	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),

	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),

	QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),

};



static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),

};



static const struct qmp_phy_init_tbl msm8996_pcie_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),

	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
@@ -1593,6 +1668,30 @@ static const char * const qmp_phy_vreg_l[] = { 
	"vdda-phy", "vdda-pll",

};



static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {

	.type			= PHY_TYPE_USB3,

	.nlanes			= 1,



	.serdes_tbl		= ipq8074_usb3_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(ipq8074_usb3_serdes_tbl),

	.tx_tbl			= msm8996_usb3_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(msm8996_usb3_tx_tbl),

	.rx_tbl			= ipq8074_usb3_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(ipq8074_usb3_rx_tbl),

	.pcs_tbl		= ipq8074_usb3_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(ipq8074_usb3_pcs_tbl),

	.clk_list		= msm8996_phy_clk_l,

	.num_clks		= ARRAY_SIZE(msm8996_phy_clk_l),

	.reset_list		= msm8996_usb3phy_reset_l,

	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),

	.vreg_list		= qmp_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),

	.regs			= usb3phy_regs_layout,



	.start_ctrl		= SERDES_START | PCS_START,

	.pwrdn_ctrl		= SW_PWRDN,

};



static const struct qmp_phy_cfg msm8996_pciephy_cfg = {

	.type			= PHY_TYPE_PCIE,

	.nlanes			= 3,
@@ -2699,6 +2798,9 @@ int qcom_qmp_phy_create(struct device *dev, struct device_node *np, int id) 


static const struct of_device_id qcom_qmp_phy_of_match_table[] = {

	{

		.compatible = "qcom,ipq8074-qmp-usb3-phy",

		.data = &ipq8074_usb3phy_cfg,

	}, {

		.compatible = "qcom,msm8996-qmp-pcie-phy",

		.data = &msm8996_pciephy_cfg,

	}, {