Commit 504ee236 authored by Marc Zyngier's avatar Marc Zyngier Committed by Will Deacon
Browse files

arm64: Add the arm64.nosve command line option 



In order to be able to completely disable SVE even if the HW
seems to support it (most likely because the FW is broken),
move the SVE setup into the EL2 finalisation block, and
use a new idreg override to deal with it.

Note that we also nuke id_aa64zfr0_el1 as a byproduct, and
that SME also gets disabled, due to the dependency between the
two features.

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220630160500.1536744-9-maz@kernel.org


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent b3000e21

Documentation/admin-guide/kernel-parameters.txt

+3 −0
Original line number Diff line number Diff line
@@ -400,6 +400,9 @@ 
	arm64.nomte	[ARM64] Unconditionally disable Memory Tagging Extension

			support



	arm64.nosve	[ARM64] Unconditionally disable Scalable Vector

			Extension support



	arm64.nosme	[ARM64] Unconditionally disable Scalable Matrix

			Extension support

arch/arm64/include/asm/cpufeature.h

+2 −0
Original line number Diff line number Diff line
@@ -908,7 +908,9 @@ static inline unsigned int get_vmid_bits(u64 mmfr1) 
}



extern struct arm64_ftr_override id_aa64mmfr1_override;

extern struct arm64_ftr_override id_aa64pfr0_override;

extern struct arm64_ftr_override id_aa64pfr1_override;

extern struct arm64_ftr_override id_aa64zfr0_override;

extern struct arm64_ftr_override id_aa64smfr0_override;

extern struct arm64_ftr_override id_aa64isar1_override;

extern struct arm64_ftr_override id_aa64isar2_override;

arch/arm64/include/asm/el2_setup.h

+0 −15
Original line number Diff line number Diff line
@@ -129,20 +129,6 @@ 
	msr	cptr_el2, x0			// Disable copro. traps to EL2

.endm



/* SVE register access */

.macro __init_el2_nvhe_sve

	mrs	x1, id_aa64pfr0_el1

	ubfx	x1, x1, #ID_AA64PFR0_SVE_SHIFT, #4

	cbz	x1, .Lskip_sve_\@



	bic	x0, x0, #CPTR_EL2_TZ		// Also disable SVE traps

	msr	cptr_el2, x0			// Disable copro. traps to EL2

	isb

	mov	x1, #ZCR_ELx_LEN_MASK		// SVE: Enable full vector

	msr_s	SYS_ZCR_EL2, x1			// length for EL1.

.Lskip_sve_\@:

.endm



/* Disable any fine grained traps */

.macro __init_el2_fgt

	mrs	x1, id_aa64mmfr0_el1
@@ -206,7 +192,6 @@ 
	__init_el2_hstr

	__init_el2_nvhe_idregs

	__init_el2_nvhe_cptr

	__init_el2_nvhe_sve

	__init_el2_fgt

	__init_el2_nvhe_prepare_eret

.endm

arch/arm64/kernel/cpufeature.c

+6 −2
Original line number Diff line number Diff line
@@ -631,7 +631,9 @@ static const struct arm64_ftr_bits ftr_raz[] = { 
	__ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override)



struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override;

struct arm64_ftr_override __ro_after_init id_aa64pfr0_override;

struct arm64_ftr_override __ro_after_init id_aa64pfr1_override;

struct arm64_ftr_override __ro_after_init id_aa64zfr0_override;

struct arm64_ftr_override __ro_after_init id_aa64smfr0_override;

struct arm64_ftr_override __ro_after_init id_aa64isar1_override;

struct arm64_ftr_override __ro_after_init id_aa64isar2_override;
@@ -669,10 +671,12 @@ static const struct __ftr_reg_entry { 
	ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),



	/* Op1 = 0, CRn = 0, CRm = 4 */

	ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),

	ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0,

			       &id_aa64pfr0_override),

	ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1,

			       &id_aa64pfr1_override),

	ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),

	ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0,

			       &id_aa64zfr0_override),

	ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0,

			       &id_aa64smfr0_override),

arch/arm64/kernel/hyp-stub.S

+11 −0
Original line number Diff line number Diff line
@@ -98,6 +98,17 @@ SYM_CODE_START_LOCAL(elx_sync) 
SYM_CODE_END(elx_sync)



SYM_CODE_START_LOCAL(__finalise_el2)

	check_override id_aa64pfr0 ID_AA64PFR0_SVE_SHIFT .Linit_sve .Lskip_sve



.Linit_sve:	/* SVE register access */

	mrs	x0, cptr_el2			// Disable SVE traps

	bic	x0, x0, #CPTR_EL2_TZ

	msr	cptr_el2, x0

	isb

	mov	x1, #ZCR_ELx_LEN_MASK		// SVE: Enable full vector

	msr_s	SYS_ZCR_EL2, x1			// length for EL1.



.Lskip_sve:

	check_override id_aa64pfr1 ID_AA64PFR1_SME_SHIFT .Linit_sme .Lskip_sme



.Linit_sme:	/* SME register access and priority mapping */