Commit 5047ab95 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Rob Clark
Browse files

drm/msm/dsi_pll_7nm: restore VCO rate during restore_state 



PHY disable/enable resets PLL registers to default values. Thus in
addition to restoring several registers we also need to restore VCO rate
settings.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: 1ef7c99d ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 91693cbc

drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c

+8 −0
Original line number Diff line number Diff line
@@ -585,6 +585,7 @@ static int dsi_pll_7nm_restore_state(struct msm_dsi_pll *pll) 
	struct pll_7nm_cached_state *cached = &pll_7nm->cached_state;

	void __iomem *phy_base = pll_7nm->phy_cmn_mmio;

	u32 val;

	int ret;



	val = pll_read(pll_7nm->mmio + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);

	val &= ~0x3;
@@ -599,6 +600,13 @@ static int dsi_pll_7nm_restore_state(struct msm_dsi_pll *pll) 
	val |= cached->pll_mux;

	pll_write(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, val);



	ret = dsi_pll_7nm_vco_set_rate(&pll->clk_hw, pll_7nm->vco_current_rate, pll_7nm->vco_ref_clk_rate);

	if (ret) {

		DRM_DEV_ERROR(&pll_7nm->pdev->dev,

			"restore vco rate failed. ret=%d\n", ret);

		return ret;

	}



	DBG("DSI PLL%d", pll_7nm->id);



	return 0;