Commit 5005e981 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'amd-drm-fixes-5.18-2022-05-11' of... 

Merge tag 'amd-drm-fixes-5.18-2022-05-11' of https://gitlab.freedesktop.org/agd5f/linux

 into drm-fixes

amd-drm-fixes-5.18-2022-05-11:

amdgpu:
- Disable ASPM for VI boards on ADL platforms
- S0ix DCN3.1 display fix
- Resume regression fix
- Stable pstate fix

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220511174422.5769-1-alexander.deucher@amd.com
parents c8f0c2d4 c65b364c

drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c

+5 −0
Original line number Diff line number Diff line
@@ -296,6 +296,7 @@ static int amdgpu_ctx_set_stable_pstate(struct amdgpu_ctx *ctx, 
{

	struct amdgpu_device *adev = ctx->adev;

	enum amd_dpm_forced_level level;

	u32 current_stable_pstate;

	int r;



	mutex_lock(&adev->pm.stable_pstate_ctx_lock);
@@ -304,6 +305,10 @@ static int amdgpu_ctx_set_stable_pstate(struct amdgpu_ctx *ctx, 
		goto done;

	}



	r = amdgpu_ctx_get_stable_pstate(ctx, &current_stable_pstate);

	if (r || (stable_pstate == current_stable_pstate))

		goto done;



	switch (stable_pstate) {

	case AMDGPU_CTX_STABLE_PSTATE_NONE:

		level = AMD_DPM_FORCED_LEVEL_AUTO;

drivers/gpu/drm/amd/amdgpu/vi.c

+16 −1
Original line number Diff line number Diff line
@@ -81,6 +81,10 @@ 
#include "mxgpu_vi.h"

#include "amdgpu_dm.h"



#if IS_ENABLED(CONFIG_X86)

#include <asm/intel-family.h>

#endif



#define ixPCIE_LC_L1_PM_SUBSTATE	0x100100C6

#define PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK	0x00000001L

#define PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK	0x00000002L
@@ -1134,13 +1138,24 @@ static void vi_enable_aspm(struct amdgpu_device *adev) 
		WREG32_PCIE(ixPCIE_LC_CNTL, data);

}



static bool aspm_support_quirk_check(void)

{

#if IS_ENABLED(CONFIG_X86)

	struct cpuinfo_x86 *c = &cpu_data(0);



	return !(c->x86 == 6 && c->x86_model == INTEL_FAM6_ALDERLAKE);

#else

	return true;

#endif

}



static void vi_program_aspm(struct amdgpu_device *adev)

{

	u32 data, data1, orig;

	bool bL1SS = false;

	bool bClkReqSupport = true;



	if (!amdgpu_device_should_use_aspm(adev))

	if (!amdgpu_device_should_use_aspm(adev) || !aspm_support_quirk_check())

		return;



	if (adev->flags & AMD_IS_APU ||

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_init.c

+0 −5
Original line number Diff line number Diff line
@@ -153,9 +153,4 @@ void dcn31_hw_sequencer_construct(struct dc *dc) 
		dc->hwss.init_hw = dcn20_fpga_init_hw;

		dc->hwseq->funcs.init_pipes = NULL;

	}

	if (dc->debug.disable_z10) {

		/*hw not support z10 or sw disable it*/

		dc->hwss.z10_restore = NULL;

		dc->hwss.z10_save_init = NULL;

	}

}

drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

+1 −7
Original line number Diff line number Diff line
@@ -1351,14 +1351,8 @@ static int smu_disable_dpms(struct smu_context *smu) 
{

	struct amdgpu_device *adev = smu->adev;

	int ret = 0;

	/*

	 * TODO: (adev->in_suspend && !adev->in_s0ix) is added to pair

	 * the workaround which always reset the asic in suspend.

	 * It's likely that workaround will be dropped in the future.

	 * Then the change here should be dropped together.

	 */

	bool use_baco = !smu->is_apu &&

		(((amdgpu_in_reset(adev) || (adev->in_suspend && !adev->in_s0ix)) &&

		((amdgpu_in_reset(adev) &&

		  (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||

		 ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));