Unverified Commit 4fb36a02 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!2704 crypto: hisilicon - round some bugfixes 

Merge Pull Request from: @xiao_jiang_shui 
 
* issue: https://gitee.com/openeuler/kernel/issues/I8B6T4 
 
Link:https://gitee.com/openeuler/kernel/pulls/2704

 

Reviewed-by: default avatarYang Shen <shenyang39@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents 7b6c5fb1 4d4c15c4

drivers/crypto/hisilicon/hpre/hpre_main.c

+1 −1
Original line number Diff line number Diff line
@@ -1010,7 +1010,7 @@ static int hpre_cluster_debugfs_init(struct hisi_qm *qm) 


	for (i = 0; i < clusters_num; i++) {

		ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i);

		if (ret < 0)

		if (ret >= HPRE_DBGFS_VAL_MAX_LEN)

			return -EINVAL;

		tmp_d = debugfs_create_dir(buf, qm->debug.debug_root);

drivers/crypto/hisilicon/qm.c

+9 −1
Original line number Diff line number Diff line
@@ -71,6 +71,7 @@ 


#define QM_AEQE_PHASE(aeqe)		((le32_to_cpu((aeqe)->dw0) >> 16) & 0x1)

#define QM_AEQE_TYPE_SHIFT		17

#define QM_AEQE_TYPE_MASK		0xf

#define QM_AEQE_CQN_MASK		GENMASK(15, 0)

#define QM_CQ_OVERFLOW			0

#define QM_EQ_OVERFLOW			1
@@ -90,6 +91,8 @@ 
#define QM_DB_PRIORITY_SHIFT_V1		48

#define QM_PAGE_SIZE			0x0034

#define QM_QP_DB_INTERVAL		0x10000

#define QM_DB_TIMEOUT_CFG		0x100074

#define QM_DB_TIMEOUT_SET		0x1fffff



#define QM_MEM_START_INIT		0x100040

#define QM_MEM_INIT_DONE		0x100044
@@ -1186,7 +1189,8 @@ static irqreturn_t qm_aeq_thread(int irq, void *data) 
	atomic64_inc(&qm->debug.dfx.aeq_irq_cnt);



	while (QM_AEQE_PHASE(aeqe) == qm->status.aeqc_phase) {

		type = le32_to_cpu(aeqe->dw0) >> QM_AEQE_TYPE_SHIFT;

		type = (le32_to_cpu(aeqe->dw0) >> QM_AEQE_TYPE_SHIFT) &

			QM_AEQE_TYPE_MASK;

		qp_id = le32_to_cpu(aeqe->dw0) & QM_AEQE_CQN_MASK;



		switch (type) {
@@ -5626,6 +5630,8 @@ int hisi_qm_init(struct hisi_qm *qm) 
		goto err_pci_init;



	if (qm->fun_type == QM_HW_PF) {

		/* Set the doorbell timeout to QM_DB_TIMEOUT_CFG ns. */

		writel(QM_DB_TIMEOUT_SET, qm->io_base + QM_DB_TIMEOUT_CFG);

		qm_disable_clock_gate(qm);

		ret = qm_dev_mem_reset(qm);

		if (ret) {
@@ -5793,6 +5799,8 @@ static int qm_rebuild_for_resume(struct hisi_qm *qm) 


	qm_cmd_init(qm);

	hisi_qm_dev_err_init(qm);

	/* Set the doorbell timeout to QM_DB_TIMEOUT_CFG ns. */

	writel(QM_DB_TIMEOUT_SET, qm->io_base + QM_DB_TIMEOUT_CFG);

	qm_disable_clock_gate(qm);

	ret = qm_dev_mem_reset(qm);

	if (ret)

drivers/crypto/hisilicon/sec/sec_drv.c

+2 −2
Original line number Diff line number Diff line
@@ -1107,8 +1107,8 @@ static int sec_queue_res_cfg(struct sec_queue *queue) 
	}

	queue->task_irq = platform_get_irq(to_platform_device(dev),

					   queue->queue_id * 2 + 1);

	if (queue->task_irq <= 0) {

		ret = -EINVAL;

	if (queue->task_irq < 0) {

		ret = queue->task_irq;

		goto err_free_ring_db;

	}