Commit 4f4b8f8f authored by Marc Zyngier's avatar Marc Zyngier
Browse files

Merge branch irq/affinity-nosmp into irq/plic-masking 



* irq/affinity-nosmp:
  : .
  : non-SMP IRQ affinity fixes courtesy of Samuel Holland:
  :
  : "This series solves some inconsistency with how IRQ affinity masks are
  : handled between SMP and non-SMP configurations.
  :
  : In non-SMP configs, an IRQ's true affinity is always cpumask_of(0), so
  : irq_{,data_}get_affinity_mask now return that, instead of returning an
  : uninitialized per-IRQ cpumask. This change makes iterating over the
  : affinity mask do the right thing in both SMP and non-SMP configurations.
  :
  : To accomplish that:
  :  - patches 1-3 disable some library code that was broken anyway on !SMP
  :  - patches 4-7 refactor the code so that irq_{,data_}get_affinity_mask
  :    can return a const cpumask, since that is what cpumask_of provides
  :  - patch 8 drops the per-IRQ cpumask and replaces it with cpumask_of(0)"
  : .
  PCI: hv: Take a const cpumask in hv_compose_msi_req_get_cpu()
  genirq: Provide an IRQ affinity mask in non-SMP configs
  genirq: Return a const cpumask from irq_data_get_affinity_mask
  genirq: Add and use an irq_data_update_affinity helper
  genirq: Refactor accessors to use irq_data_get_affinity_mask
  genirq: Drop redundant irq_init_effective_affinity
  genirq: GENERIC_IRQ_EFFECTIVE_AFF_MASK depends on SMP
  genirq: GENERIC_IRQ_IPI depends on SMP
  irqchip/mips-gic: Only register IPI domain when SMP is enabled

Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parents ee4aae57 9167fd5d

arch/alpha/kernel/irq.c

+1 −1
Original line number Diff line number Diff line
@@ -60,7 +60,7 @@ int irq_select_affinity(unsigned int irq) 
		cpu = (cpu < (NR_CPUS-1) ? cpu + 1 : 0);

	last_cpu = cpu;



	cpumask_copy(irq_data_get_affinity_mask(data), cpumask_of(cpu));

	irq_data_update_affinity(data, cpumask_of(cpu));

	chip->irq_set_affinity(data, cpumask_of(cpu), false);

	return 0;

}

arch/arm/mach-hisi/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@ config ARCH_HIP04 
	select HAVE_ARM_ARCH_TIMER

	select MCPM if SMP

	select MCPM_QUAD_CLUSTER if SMP

	select GENERIC_IRQ_EFFECTIVE_AFF_MASK

	select GENERIC_IRQ_EFFECTIVE_AFF_MASK if SMP

	help

	  Support for Hisilicon HiP04 SoC family

arch/ia64/kernel/iosapic.c

+1 −1
Original line number Diff line number Diff line
@@ -834,7 +834,7 @@ iosapic_unregister_intr (unsigned int gsi) 
	if (iosapic_intr_info[irq].count == 0) {

#ifdef CONFIG_SMP

		/* Clear affinity */

		cpumask_setall(irq_get_affinity_mask(irq));

		irq_data_update_affinity(irq_get_irq_data(irq), cpu_all_mask);

#endif

		/* Clear the interrupt information */

		iosapic_intr_info[irq].dest = 0;

arch/ia64/kernel/irq.c

+2 −2
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ static char irq_redir [NR_IRQS]; // = { [0 ... NR_IRQS-1] = 1 }; 
void set_irq_affinity_info (unsigned int irq, int hwid, int redir)

{

	if (irq < NR_IRQS) {

		cpumask_copy(irq_get_affinity_mask(irq),

		irq_data_update_affinity(irq_get_irq_data(irq),

					 cpumask_of(cpu_logical_id(hwid)));

		irq_redir[irq] = (char) (redir & 0xff);

	}

arch/ia64/kernel/msi_ia64.c

+2 −2
Original line number Diff line number Diff line
@@ -37,7 +37,7 @@ static int ia64_set_msi_irq_affinity(struct irq_data *idata, 
	msg.data = data;



	pci_write_msi_msg(irq, &msg);

	cpumask_copy(irq_data_get_affinity_mask(idata), cpumask_of(cpu));

	irq_data_update_affinity(idata, cpumask_of(cpu));



	return 0;

}
@@ -132,7 +132,7 @@ static int dmar_msi_set_affinity(struct irq_data *data, 
	msg.address_lo |= MSI_ADDR_DEST_ID_CPU(cpu_physical_id(cpu));



	dmar_msi_write(irq, &msg);

	cpumask_copy(irq_data_get_affinity_mask(data), mask);

	irq_data_update_affinity(data, mask);



	return 0;

}