Commit 4f374d2c authored by Stefan Chulski's avatar Stefan Chulski Committed by Jakub Kicinski
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net: mvpp2: fix pkt coalescing int-threshold configuration 



The packet coalescing interrupt threshold has separated registers
for different aggregated/cpu (sw-thread). The required value should
be loaded for every thread but not only for 1 current cpu.

Fixes: 213f428f ("net: mvpp2: add support for TX interrupts and RX queue distribution modes")
Signed-off-by: default avatarStefan Chulski <stefanc@marvell.com>
Link: https://lore.kernel.org/r/1608748521-11033-1-git-send-email-stefanc@marvell.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent bb2cc7d7

drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c

+6 −5
Original line number Diff line number Diff line
@@ -2370,17 +2370,18 @@ static void mvpp2_rx_pkts_coal_set(struct mvpp2_port *port, 
static void mvpp2_tx_pkts_coal_set(struct mvpp2_port *port,

				   struct mvpp2_tx_queue *txq)

{

	unsigned int thread = mvpp2_cpu_to_thread(port->priv, get_cpu());

	unsigned int thread;

	u32 val;



	if (txq->done_pkts_coal > MVPP2_TXQ_THRESH_MASK)

		txq->done_pkts_coal = MVPP2_TXQ_THRESH_MASK;



	val = (txq->done_pkts_coal << MVPP2_TXQ_THRESH_OFFSET);

	/* PKT-coalescing registers are per-queue + per-thread */

	for (thread = 0; thread < MVPP2_MAX_THREADS; thread++) {

		mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_NUM_REG, txq->id);

		mvpp2_thread_write(port->priv, thread, MVPP2_TXQ_THRESH_REG, val);



	put_cpu();

	}

}



static u32 mvpp2_usec_to_cycles(u32 usec, unsigned long clk_hz)