Unverified Commit 4f2f2991 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v6.3-next-soc' of... 

Merge tag 'v6.3-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into soc/drivers

mtk-svs:
smaller coding style changes

mtk-mutex:
- add support for mt8365 display and mt8195 VPP mutex
- add support for more then 32 mods
- use module_platform_driver instead of open coding

mtk-mmsys:
- add support for mt8195 RSZ switching
- add remove function
- use module_platform_driver instead of open coding
- split out mt8173 routing table from the legacy table
- bump up resets in mt8173 to 64
- add support for mt6795 (Helio X10)
- clean-up IS_REACHABLE code for cmdq

* tag 'v6.3-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: (25 commits)
  soc: mediatek: Kconfig: Add MTK_CMDQ dependency to MTK_MMSYS
  soc: mediatek: mutex: Use dev_err_probe()
  soc: mediatek: mtk-mmsys: Add support for MT6795 Helio X10
  soc: mediatek: mtk-mmsys: Change MT8173 num_resets to 64
  soc: mediatek: mtk-mmsys: Split out MT8173 mmsys DDP routing table
  soc: mediatek: Cleanup ifdefs for IS_REACHABLE(CONFIG_MTK_CMDQ)
  soc: mediatek: cmdq: Add inline functions for !CONFIG_MTK_CMDQ
  soc: mediatek: mtk-mutex: Use module_platform_driver() macro
  soc: mediatek: mtk-mutex: Replace max handles number with definition
  soc: mediatek: mtk-mutex: Compress of_device_id array entries
  soc: mediatek: mtk-mmsys: Add MODULE_DEVICE_TABLE() to allow auto-load
  soc: mediatek: mtk-mmsys: Compress of_device_id array entries
  soc: mediatek: mtk-mmsys: Use module_platform_driver() macro
  soc: mediatek: mtk-mmsys: Add .remove() callback
  dt-bindings: soc: mediatek: add display mutex for MT8365 SoC
  dt-bindings: soc: mediatek: specify which compatible requires clocks property
  soc: mediatek: mtk-svs: add thermal voltage compensation if needed
  soc: mediatek: mtk-svs: fix passing zero to 'PTR_ERR'
  soc: mediatek: mtk-svs: delete node name check
  soc: mediatek: mutex: support MT8195 VPPSYS
  ...

Link: https://lore.kernel.org/r/bc9f7a74-ce12-b323-021c-ff2c0473e979@gmail.com


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 04523ace 5ce5e0d0

Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml

+21 −1
Original line number Diff line number Diff line
@@ -35,6 +35,8 @@ properties: 
      - mediatek,mt8188-disp-mutex

      - mediatek,mt8192-disp-mutex

      - mediatek,mt8195-disp-mutex

      - mediatek,mt8195-vpp-mutex

      - mediatek,mt8365-disp-mutex



  reg:

    maxItems: 1
@@ -70,12 +72,30 @@ properties: 
      4 arguments defined in this property. Each GCE subsys id is mapping to

      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - mediatek,mt2701-disp-mutex

              - mediatek,mt2712-disp-mutex

              - mediatek,mt6795-disp-mutex

              - mediatek,mt8173-disp-mutex

              - mediatek,mt8186-disp-mutex

              - mediatek,mt8186-mdp3-mutex

              - mediatek,mt8192-disp-mutex

              - mediatek,mt8195-disp-mutex

    then:

      required:

        - clocks





required:

  - compatible

  - reg

  - interrupts

  - power-domains

  - clocks



additionalProperties: false

drivers/soc/mediatek/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ config MTK_MMSYS 
	tristate "MediaTek MMSYS Support"

	default ARCH_MEDIATEK

	depends on HAS_IOMEM

	depends on MTK_CMDQ || MTK_CMDQ=n

	help

	  Say yes here to add support for the MediaTek Multimedia

	  Subsystem (MMSYS).

drivers/soc/mediatek/mt8173-mmsys.h

0 → 100644
+95 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */



#ifndef __SOC_MEDIATEK_MT8173_MMSYS_H

#define __SOC_MEDIATEK_MT8173_MMSYS_H



#define MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040

#define MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044

#define MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048

#define MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c

#define MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050

#define MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084

#define MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088

#define MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN		0x08c

#define MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN		0x0a0

#define MT8173_DISP_REG_CONFIG_DSI0_SEL_IN		0x0a4

#define MT8173_DISP_REG_CONFIG_DPI_SEL_IN		0x0ac

#define MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN	0x0b0

#define MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8

#define MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN	0x0bc



#define MT8173_AAL_SEL_IN_MERGE				BIT(0)

#define MT8173_COLOR0_SEL_IN_OVL0			BIT(0)

#define MT8173_COLOR0_SOUT_MERGE			BIT(0)

#define MT8173_DPI0_SEL_IN_MASK				GENMASK(1, 0)

#define MT8173_DPI0_SEL_IN_RDMA1			BIT(0)

#define MT8173_DSI0_SEL_IN_UFOE				BIT(0)

#define MT8173_GAMMA_MOUT_EN_RDMA1			BIT(0)

#define MT8173_OD0_MOUT_EN_RDMA0			BIT(0)

#define MT8173_OVL0_MOUT_EN_COLOR0			BIT(0)

#define MT8173_OVL1_MOUT_EN_COLOR1			BIT(0)

#define MT8173_UFOE_MOUT_EN_DSI0			BIT(0)

#define MT8173_UFOE_SEL_IN_RDMA0			BIT(0)

#define MT8173_RDMA0_SOUT_COLOR0			BIT(0)



static const struct mtk_mmsys_routes mt8173_mmsys_routing_table[] = {

	{

		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,

		MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,

		MT8173_OVL0_MOUT_EN_COLOR0, MT8173_OVL0_MOUT_EN_COLOR0

	}, {

		DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,

		MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN,

		MT8173_OD0_MOUT_EN_RDMA0, MT8173_OD0_MOUT_EN_RDMA0

	}, {

		DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,

		MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN,

		MT8173_UFOE_MOUT_EN_DSI0, MT8173_UFOE_MOUT_EN_DSI0

	}, {

		DDP_COMPONENT_COLOR0, DDP_COMPONENT_AAL0,

		MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN,

		MT8173_COLOR0_SOUT_MERGE, 0 /* SOUT to AAL */

	}, {

		DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE,

		MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN,

		MT8173_RDMA0_SOUT_COLOR0, 0 /* SOUT to UFOE */

	}, {

		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,

		MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,

		MT8173_COLOR0_SEL_IN_OVL0, MT8173_COLOR0_SEL_IN_OVL0

	}, {

		DDP_COMPONENT_AAL0, DDP_COMPONENT_COLOR0,

		MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN,

		MT8173_AAL_SEL_IN_MERGE, 0 /* SEL_IN from COLOR0 */

	}, {

		DDP_COMPONENT_RDMA0, DDP_COMPONENT_UFOE,

		MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN,

		MT8173_UFOE_SEL_IN_RDMA0, 0 /* SEL_IN from RDMA0 */

	}, {

		DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,

		MT8173_DISP_REG_CONFIG_DSI0_SEL_IN,

		MT8173_DSI0_SEL_IN_UFOE, 0, /* SEL_IN from UFOE */

	}, {

		DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,

		MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN,

		MT8173_OVL1_MOUT_EN_COLOR1, MT8173_OVL1_MOUT_EN_COLOR1

	}, {

		DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,

		MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN,

		MT8173_GAMMA_MOUT_EN_RDMA1, MT8173_GAMMA_MOUT_EN_RDMA1

	}, {

		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,

		MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN,

		RDMA1_SOUT_MASK, RDMA1_SOUT_DPI0

	}, {

		DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,

		MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN,

		COLOR1_SEL_IN_OVL1, COLOR1_SEL_IN_OVL1

	}, {

		DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,

		MT8173_DISP_REG_CONFIG_DPI_SEL_IN,

		MT8173_DPI0_SEL_IN_MASK, MT8173_DPI0_SEL_IN_RDMA1

	}

};



#endif /* __SOC_MEDIATEK_MT8173_MMSYS_H */

drivers/soc/mediatek/mt8195-mmsys.h

+13 −0
Original line number Diff line number Diff line
@@ -146,6 +146,19 @@ 
#define MT8195_VDO1_MIXER_SOUT_SEL_IN				0xf68

#define MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER			0



/* VPPSYS1 */

#define MT8195_VPP1_HW_DCM_1ST_DIS0				0x150

#define MT8195_VPP1_HW_DCM_1ST_DIS1				0x160

#define MT8195_VPP1_HW_DCM_2ND_DIS0				0x1a0

#define MT8195_VPP1_HW_DCM_2ND_DIS1				0x1b0

#define MT8195_SVPP2_BUF_BF_RSZ_SWITCH				0xf48

#define MT8195_SVPP3_BUF_BF_RSZ_SWITCH				0xf74



/* VPPSYS1 HW DCM client*/

#define MT8195_SVPP1_MDP_RSZ					BIT(25)

#define MT8195_SVPP2_MDP_RSZ					BIT(4)

#define MT8195_SVPP3_MDP_RSZ					BIT(5)



static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {

	{

		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,

drivers/soc/mediatek/mtk-mmsys.c

+101 −94
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ 


#include "mtk-mmsys.h"

#include "mt8167-mmsys.h"

#include "mt8173-mmsys.h"

#include "mt8183-mmsys.h"

#include "mt8186-mmsys.h"

#include "mt8188-mmsys.h"
@@ -40,6 +41,14 @@ static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = { 
	.clk_driver = "clk-mt6779-mm",

};



static const struct mtk_mmsys_driver_data mt6795_mmsys_driver_data = {

	.clk_driver = "clk-mt6795-mm",

	.routes = mt8173_mmsys_routing_table,

	.num_routes = ARRAY_SIZE(mt8173_mmsys_routing_table),

	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,

	.num_resets = 64,

};



static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {

	.clk_driver = "clk-mt6797-mm",

};
@@ -52,10 +61,10 @@ static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = { 


static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {

	.clk_driver = "clk-mt8173-mm",

	.routes = mmsys_default_routing_table,

	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),

	.routes = mt8173_mmsys_routing_table,

	.num_routes = ARRAY_SIZE(mt8173_mmsys_routing_table),

	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,

	.num_resets = 32,

	.num_resets = 64,

};



static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
@@ -121,6 +130,8 @@ static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { 
struct mtk_mmsys {

	void __iomem *regs;

	const struct mtk_mmsys_driver_data *data;

	struct platform_device *clks_pdev;

	struct platform_device *drm_pdev;

	spinlock_t lock; /* protects mmsys_sw_rst_b reg */

	struct reset_controller_dev rcdev;

	struct cmdq_client_reg cmdq_base;
@@ -129,21 +140,18 @@ struct mtk_mmsys { 
static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32 offset, u32 mask, u32 val,

				  struct cmdq_pkt *cmdq_pkt)

{

	int ret;

	u32 tmp;



#if IS_REACHABLE(CONFIG_MTK_CMDQ)

	if (cmdq_pkt) {

		if (mmsys->cmdq_base.size == 0) {

			pr_err("mmsys lose gce property, failed to update mmsys bits with cmdq");

			return;

		}

		cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,

	if (mmsys->cmdq_base.size && cmdq_pkt) {

		ret = cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,

					  mmsys->cmdq_base.offset + offset, val,

					  mask);

		if (ret)

			pr_debug("CMDQ unavailable: using CPU write\n");

		else

			return;

	}

#endif



	tmp = readl_relaxed(mmsys->regs + offset);

	tmp = (tmp & ~mask) | (val & mask);

	writel_relaxed(tmp, mmsys->regs + offset);
@@ -242,6 +250,50 @@ void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val) 
}

EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_dpi_fmt_config);



void mtk_mmsys_vpp_rsz_merge_config(struct device *dev, u32 id, bool enable,

				    struct cmdq_pkt *cmdq_pkt)

{

	u32 reg;



	switch (id) {

	case 2:

		reg = MT8195_SVPP2_BUF_BF_RSZ_SWITCH;

		break;

	case 3:

		reg = MT8195_SVPP3_BUF_BF_RSZ_SWITCH;

		break;

	default:

		dev_err(dev, "Invalid id %d\n", id);

		return;

	}



	mtk_mmsys_update_bits(dev_get_drvdata(dev), reg, ~0, enable, cmdq_pkt);

}

EXPORT_SYMBOL_GPL(mtk_mmsys_vpp_rsz_merge_config);



void mtk_mmsys_vpp_rsz_dcm_config(struct device *dev, bool enable,

				  struct cmdq_pkt *cmdq_pkt)

{

	u32 client;



	client = MT8195_SVPP1_MDP_RSZ;

	mtk_mmsys_update_bits(dev_get_drvdata(dev),

			      MT8195_VPP1_HW_DCM_1ST_DIS0, client,

			      ((enable) ? client : 0), cmdq_pkt);

	mtk_mmsys_update_bits(dev_get_drvdata(dev),

			      MT8195_VPP1_HW_DCM_2ND_DIS0, client,

			      ((enable) ? client : 0), cmdq_pkt);



	client = MT8195_SVPP2_MDP_RSZ | MT8195_SVPP3_MDP_RSZ;

	mtk_mmsys_update_bits(dev_get_drvdata(dev),

			      MT8195_VPP1_HW_DCM_1ST_DIS1, client,

			      ((enable) ? client : 0), cmdq_pkt);

	mtk_mmsys_update_bits(dev_get_drvdata(dev),

			      MT8195_VPP1_HW_DCM_2ND_DIS1, client,

			      ((enable) ? client : 0), cmdq_pkt);

}

EXPORT_SYMBOL_GPL(mtk_mmsys_vpp_rsz_dcm_config);



static int mtk_mmsys_reset_update(struct reset_controller_dev *rcdev, unsigned long id,

				  bool assert)

{
@@ -330,11 +382,10 @@ static int mtk_mmsys_probe(struct platform_device *pdev) 
		}

	}



#if IS_REACHABLE(CONFIG_MTK_CMDQ)

	/* CMDQ is optional */

	ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);

	if (ret)

		dev_dbg(dev, "No mediatek,gce-client-reg!\n");

#endif



	platform_set_drvdata(pdev, mmsys);
@@ -342,6 +393,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev) 
					     PLATFORM_DEVID_AUTO, NULL, 0);

	if (IS_ERR(clks))

		return PTR_ERR(clks);

	mmsys->clks_pdev = clks;



	if (mmsys->data->is_vppsys)

		goto out_probe_done;
@@ -352,78 +404,44 @@ static int mtk_mmsys_probe(struct platform_device *pdev) 
		platform_device_unregister(clks);

		return PTR_ERR(drm);

	}

	mmsys->drm_pdev = drm;



out_probe_done:

	return 0;

}



static const struct of_device_id of_match_mtk_mmsys[] = {

	{

		.compatible = "mediatek,mt2701-mmsys",

		.data = &mt2701_mmsys_driver_data,

	},

	{

		.compatible = "mediatek,mt2712-mmsys",

		.data = &mt2712_mmsys_driver_data,

	},

	{

		.compatible = "mediatek,mt6779-mmsys",

		.data = &mt6779_mmsys_driver_data,

	},

static int mtk_mmsys_remove(struct platform_device *pdev)

{

		.compatible = "mediatek,mt6797-mmsys",

		.data = &mt6797_mmsys_driver_data,

	},

	{

		.compatible = "mediatek,mt8167-mmsys",

		.data = &mt8167_mmsys_driver_data,

	},

	{

		.compatible = "mediatek,mt8173-mmsys",

		.data = &mt8173_mmsys_driver_data,

	},

	{

		.compatible = "mediatek,mt8183-mmsys",

		.data = &mt8183_mmsys_driver_data,

	},

	{

		.compatible = "mediatek,mt8186-mmsys",

		.data = &mt8186_mmsys_driver_data,

	},

	{

		.compatible = "mediatek,mt8188-vdosys0",

		.data = &mt8188_vdosys0_driver_data,

	},

	{

		.compatible = "mediatek,mt8192-mmsys",

		.data = &mt8192_mmsys_driver_data,

	},

	{	/* deprecated compatible */

		.compatible = "mediatek,mt8195-mmsys",

		.data = &mt8195_vdosys0_driver_data,

	},

	{

		.compatible = "mediatek,mt8195-vdosys0",

		.data = &mt8195_vdosys0_driver_data,

	},

	{

		.compatible = "mediatek,mt8195-vdosys1",

		.data = &mt8195_vdosys1_driver_data,

	},

	{

		.compatible = "mediatek,mt8195-vppsys0",

		.data = &mt8195_vppsys0_driver_data,

	},

	{

		.compatible = "mediatek,mt8195-vppsys1",

		.data = &mt8195_vppsys1_driver_data,

	},

	{

		.compatible = "mediatek,mt8365-mmsys",

		.data = &mt8365_mmsys_driver_data,

	},

	{ }

	struct mtk_mmsys *mmsys = platform_get_drvdata(pdev);



	platform_device_unregister(mmsys->drm_pdev);

	platform_device_unregister(mmsys->clks_pdev);



	return 0;

}



static const struct of_device_id of_match_mtk_mmsys[] = {

	{ .compatible = "mediatek,mt2701-mmsys", .data = &mt2701_mmsys_driver_data },

	{ .compatible = "mediatek,mt2712-mmsys", .data = &mt2712_mmsys_driver_data },

	{ .compatible = "mediatek,mt6779-mmsys", .data = &mt6779_mmsys_driver_data },

	{ .compatible = "mediatek,mt6795-mmsys", .data = &mt6795_mmsys_driver_data },

	{ .compatible = "mediatek,mt6797-mmsys", .data = &mt6797_mmsys_driver_data },

	{ .compatible = "mediatek,mt8167-mmsys", .data = &mt8167_mmsys_driver_data },

	{ .compatible = "mediatek,mt8173-mmsys", .data = &mt8173_mmsys_driver_data },

	{ .compatible = "mediatek,mt8183-mmsys", .data = &mt8183_mmsys_driver_data },

	{ .compatible = "mediatek,mt8186-mmsys", .data = &mt8186_mmsys_driver_data },

	{ .compatible = "mediatek,mt8188-vdosys0", .data = &mt8188_vdosys0_driver_data },

	{ .compatible = "mediatek,mt8192-mmsys", .data = &mt8192_mmsys_driver_data },

	/* "mediatek,mt8195-mmsys" compatible is deprecated */

	{ .compatible = "mediatek,mt8195-mmsys", .data = &mt8195_vdosys0_driver_data },

	{ .compatible = "mediatek,mt8195-vdosys0", .data = &mt8195_vdosys0_driver_data },

	{ .compatible = "mediatek,mt8195-vdosys1", .data = &mt8195_vdosys1_driver_data },

	{ .compatible = "mediatek,mt8195-vppsys0", .data = &mt8195_vppsys0_driver_data },

	{ .compatible = "mediatek,mt8195-vppsys1", .data = &mt8195_vppsys1_driver_data },

	{ .compatible = "mediatek,mt8365-mmsys", .data = &mt8365_mmsys_driver_data },

	{ /* sentinel */ }

};

MODULE_DEVICE_TABLE(of, of_match_mtk_mmsys);



static struct platform_driver mtk_mmsys_drv = {

	.driver = {
@@ -431,20 +449,9 @@ static struct platform_driver mtk_mmsys_drv = { 
		.of_match_table = of_match_mtk_mmsys,

	},

	.probe = mtk_mmsys_probe,

	.remove = mtk_mmsys_remove,

};



static int __init mtk_mmsys_init(void)

{

	return platform_driver_register(&mtk_mmsys_drv);

}



static void __exit mtk_mmsys_exit(void)

{

	platform_driver_unregister(&mtk_mmsys_drv);

}



module_init(mtk_mmsys_init);

module_exit(mtk_mmsys_exit);

module_platform_driver(mtk_mmsys_drv);



MODULE_AUTHOR("Yongqiang Niu <yongqiang.niu@mediatek.com>");

MODULE_DESCRIPTION("MediaTek SoC MMSYS driver");