Commit 4f2a6726 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Greg Kroah-Hartman
Browse files

coresight: etm4x: Add commentary on the registers 

As we are about define a switch..case table for individual register
access by offset for implementing the system instruction support,
document the possible set of registers for each group to make
it easier to correlate.

Link: https://lore.kernel.org/r/20210110224850.1880240-11-suzuki.poulose@arm.com


Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20210201181351.1475223-13-mathieu.poirier@linaro.org


Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent c03ceec1

drivers/hwtracing/coresight/coresight-etm4x.h

+13 −8
Original line number Diff line number Diff line
@@ -45,13 +45,13 @@ 
#define TRCVDSACCTLR			0x0A4

#define TRCVDARCCTLR			0x0A8

/* Derived resources registers */

#define TRCSEQEVRn(n)			(0x100 + (n * 4))

#define TRCSEQEVRn(n)			(0x100 + (n * 4)) /* n = 0-2 */

#define TRCSEQRSTEVR			0x118

#define TRCSEQSTR			0x11C

#define TRCEXTINSELR			0x120

#define TRCCNTRLDVRn(n)			(0x140 + (n * 4))

#define TRCCNTCTLRn(n)			(0x150 + (n * 4))

#define TRCCNTVRn(n)			(0x160 + (n * 4))

#define TRCCNTRLDVRn(n)			(0x140 + (n * 4)) /* n = 0-3 */

#define TRCCNTCTLRn(n)			(0x150 + (n * 4)) /* n = 0-3 */

#define TRCCNTVRn(n)			(0x160 + (n * 4)) /* n = 0-3 */

/* ID registers */

#define TRCIDR8				0x180

#define TRCIDR9				0x184
@@ -60,7 +60,7 @@ 
#define TRCIDR12			0x190

#define TRCIDR13			0x194

#define TRCIMSPEC0			0x1C0

#define TRCIMSPECn(n)			(0x1C0 + (n * 4))

#define TRCIMSPECn(n)			(0x1C0 + (n * 4)) /* n = 1-7 */

#define TRCIDR0				0x1E0

#define TRCIDR1				0x1E4

#define TRCIDR2				0x1E8
@@ -69,9 +69,12 @@ 
#define TRCIDR5				0x1F4

#define TRCIDR6				0x1F8

#define TRCIDR7				0x1FC

/* Resource selection registers */

/*

 * Resource selection registers, n = 2-31.

 * First pair (regs 0, 1) is always present and is reserved.

 */

#define TRCRSCTLRn(n)			(0x200 + (n * 4))

/* Single-shot comparator registers */

/* Single-shot comparator registers, n = 0-7 */

#define TRCSSCCRn(n)			(0x280 + (n * 4))

#define TRCSSCSRn(n)			(0x2A0 + (n * 4))

#define TRCSSPCICRn(n)			(0x2C0 + (n * 4))
@@ -81,11 +84,13 @@ 
#define TRCPDCR				0x310

#define TRCPDSR				0x314

/* Trace registers (0x318-0xEFC) */

/* Comparator registers */

/* Address Comparator registers n = 0-15 */

#define TRCACVRn(n)			(0x400 + (n * 8))

#define TRCACATRn(n)			(0x480 + (n * 8))

/* Data Value Comparator Value registers, n = 0-7 */

#define TRCDVCVRn(n)			(0x500 + (n * 16))

#define TRCDVCMRn(n)			(0x580 + (n * 16))

/* ContextID/Virtual ContextID comparators, n = 0-7 */

#define TRCCIDCVRn(n)			(0x600 + (n * 8))

#define TRCVMIDCVRn(n)			(0x640 + (n * 8))

#define TRCCIDCCTLR0			0x680