Commit 4f05223a authored by Ricardo Koller's avatar Ricardo Koller Committed by Marc Zyngier
Browse files

KVM: selftests: Add aarch64/debug-exceptions test 



Covers fundamental tests for debug exceptions. The guest installs and
handle its debug exceptions itself, without KVM_SET_GUEST_DEBUG.

Signed-off-by: default avatarRicardo Koller <ricarkol@google.com>
Reviewed-by: default avatarAndrew Jones <drjones@redhat.com>
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20210611011020.3420067-7-ricarkol@google.com
parent e3db7579

tools/testing/selftests/kvm/.gitignore

+1 −0
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# SPDX-License-Identifier: GPL-2.0-only

/aarch64/debug-exceptions

/aarch64/get-reg-list

/aarch64/get-reg-list-sve

/aarch64/vgic_init

tools/testing/selftests/kvm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -78,6 +78,7 @@ TEST_GEN_PROGS_x86_64 += memslot_perf_test 
TEST_GEN_PROGS_x86_64 += set_memory_region_test

TEST_GEN_PROGS_x86_64 += steal_time



TEST_GEN_PROGS_aarch64 += aarch64/debug-exceptions

TEST_GEN_PROGS_aarch64 += aarch64/get-reg-list

TEST_GEN_PROGS_aarch64 += aarch64/get-reg-list-sve

TEST_GEN_PROGS_aarch64 += aarch64/vgic_init

tools/testing/selftests/kvm/aarch64/debug-exceptions.c

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// SPDX-License-Identifier: GPL-2.0

#include <test_util.h>

#include <kvm_util.h>

#include <processor.h>



#define VCPU_ID 0



#define MDSCR_KDE	(1 << 13)

#define MDSCR_MDE	(1 << 15)

#define MDSCR_SS	(1 << 0)



#define DBGBCR_LEN8	(0xff << 5)

#define DBGBCR_EXEC	(0x0 << 3)

#define DBGBCR_EL1	(0x1 << 1)

#define DBGBCR_E	(0x1 << 0)



#define DBGWCR_LEN8	(0xff << 5)

#define DBGWCR_RD	(0x1 << 3)

#define DBGWCR_WR	(0x2 << 3)

#define DBGWCR_EL1	(0x1 << 1)

#define DBGWCR_E	(0x1 << 0)



#define SPSR_D		(1 << 9)

#define SPSR_SS		(1 << 21)



extern unsigned char sw_bp, hw_bp, bp_svc, bp_brk, hw_wp, ss_start;

static volatile uint64_t sw_bp_addr, hw_bp_addr;

static volatile uint64_t wp_addr, wp_data_addr;

static volatile uint64_t svc_addr;

static volatile uint64_t ss_addr[4], ss_idx;

#define  PC(v)  ((uint64_t)&(v))



static void reset_debug_state(void)

{

	asm volatile("msr daifset, #8");



	write_sysreg(osdlr_el1, 0);

	write_sysreg(oslar_el1, 0);

	isb();



	write_sysreg(mdscr_el1, 0);

	/* This test only uses the first bp and wp slot. */

	write_sysreg(dbgbvr0_el1, 0);

	write_sysreg(dbgbcr0_el1, 0);

	write_sysreg(dbgwcr0_el1, 0);

	write_sysreg(dbgwvr0_el1, 0);

	isb();

}



static void install_wp(uint64_t addr)

{

	uint32_t wcr;

	uint32_t mdscr;



	wcr = DBGWCR_LEN8 | DBGWCR_RD | DBGWCR_WR | DBGWCR_EL1 | DBGWCR_E;

	write_sysreg(dbgwcr0_el1, wcr);

	write_sysreg(dbgwvr0_el1, addr);

	isb();



	asm volatile("msr daifclr, #8");



	mdscr = read_sysreg(mdscr_el1) | MDSCR_KDE | MDSCR_MDE;

	write_sysreg(mdscr_el1, mdscr);

	isb();

}



static void install_hw_bp(uint64_t addr)

{

	uint32_t bcr;

	uint32_t mdscr;



	bcr = DBGBCR_LEN8 | DBGBCR_EXEC | DBGBCR_EL1 | DBGBCR_E;

	write_sysreg(dbgbcr0_el1, bcr);

	write_sysreg(dbgbvr0_el1, addr);

	isb();



	asm volatile("msr daifclr, #8");



	mdscr = read_sysreg(mdscr_el1) | MDSCR_KDE | MDSCR_MDE;

	write_sysreg(mdscr_el1, mdscr);

	isb();

}



static void install_ss(void)

{

	uint32_t mdscr;



	asm volatile("msr daifclr, #8");



	mdscr = read_sysreg(mdscr_el1) | MDSCR_KDE | MDSCR_SS;

	write_sysreg(mdscr_el1, mdscr);

	isb();

}



static volatile char write_data;



static void guest_code(void)

{

	GUEST_SYNC(0);



	/* Software-breakpoint */

	asm volatile("sw_bp: brk #0");

	GUEST_ASSERT_EQ(sw_bp_addr, PC(sw_bp));



	GUEST_SYNC(1);



	/* Hardware-breakpoint */

	reset_debug_state();

	install_hw_bp(PC(hw_bp));

	asm volatile("hw_bp: nop");

	GUEST_ASSERT_EQ(hw_bp_addr, PC(hw_bp));



	GUEST_SYNC(2);



	/* Hardware-breakpoint + svc */

	reset_debug_state();

	install_hw_bp(PC(bp_svc));

	asm volatile("bp_svc: svc #0");

	GUEST_ASSERT_EQ(hw_bp_addr, PC(bp_svc));

	GUEST_ASSERT_EQ(svc_addr, PC(bp_svc) + 4);



	GUEST_SYNC(3);



	/* Hardware-breakpoint + software-breakpoint */

	reset_debug_state();

	install_hw_bp(PC(bp_brk));

	asm volatile("bp_brk: brk #0");

	GUEST_ASSERT_EQ(sw_bp_addr, PC(bp_brk));

	GUEST_ASSERT_EQ(hw_bp_addr, PC(bp_brk));



	GUEST_SYNC(4);



	/* Watchpoint */

	reset_debug_state();

	install_wp(PC(write_data));

	write_data = 'x';

	GUEST_ASSERT_EQ(write_data, 'x');

	GUEST_ASSERT_EQ(wp_data_addr, PC(write_data));



	GUEST_SYNC(5);



	/* Single-step */

	reset_debug_state();

	install_ss();

	ss_idx = 0;

	asm volatile("ss_start:\n"

		     "mrs x0, esr_el1\n"

		     "add x0, x0, #1\n"

		     "msr daifset, #8\n"

		     : : : "x0");

	GUEST_ASSERT_EQ(ss_addr[0], PC(ss_start));

	GUEST_ASSERT_EQ(ss_addr[1], PC(ss_start) + 4);

	GUEST_ASSERT_EQ(ss_addr[2], PC(ss_start) + 8);



	GUEST_DONE();

}



static void guest_sw_bp_handler(struct ex_regs *regs)

{

	sw_bp_addr = regs->pc;

	regs->pc += 4;

}



static void guest_hw_bp_handler(struct ex_regs *regs)

{

	hw_bp_addr = regs->pc;

	regs->pstate |= SPSR_D;

}



static void guest_wp_handler(struct ex_regs *regs)

{

	wp_data_addr = read_sysreg(far_el1);

	wp_addr = regs->pc;

	regs->pstate |= SPSR_D;

}



static void guest_ss_handler(struct ex_regs *regs)

{

	GUEST_ASSERT_1(ss_idx < 4, ss_idx);

	ss_addr[ss_idx++] = regs->pc;

	regs->pstate |= SPSR_SS;

}



static void guest_svc_handler(struct ex_regs *regs)

{

	svc_addr = regs->pc;

}



static int debug_version(struct kvm_vm *vm)

{

	uint64_t id_aa64dfr0;



	get_reg(vm, VCPU_ID, ARM64_SYS_REG(ID_AA64DFR0_EL1), &id_aa64dfr0);

	return id_aa64dfr0 & 0xf;

}



int main(int argc, char *argv[])

{

	struct kvm_vm *vm;

	struct ucall uc;

	int stage;



	vm = vm_create_default(VCPU_ID, 0, guest_code);

	ucall_init(vm, NULL);



	vm_init_descriptor_tables(vm);

	vcpu_init_descriptor_tables(vm, VCPU_ID);



	if (debug_version(vm) < 6) {

		print_skip("Armv8 debug architecture not supported.");

		kvm_vm_free(vm);

		exit(KSFT_SKIP);

	}



	vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,

				ESR_EC_BRK_INS, guest_sw_bp_handler);

	vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,

				ESR_EC_HW_BP_CURRENT, guest_hw_bp_handler);

	vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,

				ESR_EC_WP_CURRENT, guest_wp_handler);

	vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,

				ESR_EC_SSTEP_CURRENT, guest_ss_handler);

	vm_install_sync_handler(vm, VECTOR_SYNC_CURRENT,

				ESR_EC_SVC64, guest_svc_handler);



	for (stage = 0; stage < 7; stage++) {

		vcpu_run(vm, VCPU_ID);



		switch (get_ucall(vm, VCPU_ID, &uc)) {

		case UCALL_SYNC:

			TEST_ASSERT(uc.args[1] == stage,

				"Stage %d: Unexpected sync ucall, got %lx",

				stage, (ulong)uc.args[1]);

			break;

		case UCALL_ABORT:

			TEST_FAIL("%s at %s:%ld\n\tvalues: %#lx, %#lx",

				(const char *)uc.args[0],

				__FILE__, uc.args[1], uc.args[2], uc.args[3]);

			break;

		case UCALL_DONE:

			goto done;

		default:

			TEST_FAIL("Unknown ucall %lu", uc.cmd);

		}

	}



done:

	kvm_vm_free(vm);

	return 0;

}

tools/testing/selftests/kvm/include/aarch64/processor.h

+16 −6
Original line number Diff line number Diff line
@@ -21,6 +21,8 @@ 
#define SCTLR_EL1               3, 0,  1, 0, 0

#define VBAR_EL1                3, 0, 12, 0, 0



#define ID_AA64DFR0_EL1         3, 0,  0, 5, 0



/*

 * Default MAIR

 *                  index   attribute
@@ -98,6 +100,12 @@ enum { 
#define ESR_EC_SHIFT		26

#define ESR_EC_MASK		(ESR_EC_NUM - 1)



#define ESR_EC_SVC64		0x15

#define ESR_EC_HW_BP_CURRENT	0x31

#define ESR_EC_SSTEP_CURRENT	0x33

#define ESR_EC_WP_CURRENT	0x35

#define ESR_EC_BRK_INS		0x3c



void vm_init_descriptor_tables(struct kvm_vm *vm);

void vcpu_init_descriptor_tables(struct kvm_vm *vm, uint32_t vcpuid);
@@ -119,4 +127,6 @@ void vm_install_sync_handler(struct kvm_vm *vm, 
	val;								  \

})



#define isb()	asm volatile("isb" : : : "memory")



#endif /* SELFTEST_KVM_PROCESSOR_H */