Commit 4eac5e72 authored by Adrien Grassein's avatar Adrien Grassein Committed by Shawn Guo
Browse files

arm64: dts: imx8mm-nitrogen-r2: add ecspi2 support 



Add the description for ecspi2 support.

Signed-off-by: default avatarAdrien Grassein <adrien.grassein@gmail.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: default avatarFabio Estevam <festevam@gmail.com>
Reviewed-by: default avatarMarco Felsch <m.felsch@pengutronix.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 307fd14d

arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts

+20 −0
Original line number Diff line number Diff line
@@ -74,6 +74,17 @@ 
	cpu-supply = <&reg_buck3>;

};



/* J15 */

&ecspi2 {

	assigned-clocks = <&clk IMX8MM_CLK_ECSPI2>;

	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_40M>;

	assigned-clock-rates = <40000000>;

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_ecspi2>;

	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;

	status = "okay";

};



&fec1 {

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_fec1>;
@@ -390,6 +401,15 @@ 
	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_hog>;



	pinctrl_ecspi2: ecspi2grp {

		fsl,pins = <

			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x140

			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x19

			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x19

			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x19

		>;

	};



	pinctrl_fec1: fec1grp {

		fsl,pins = <

			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3