Commit 4e87580e authored by James Hogan's avatar James Hogan
Browse files

MIPS: Add defs & probing of UFR 



Add definitions and probing of the UFR bit in Config5. This bit allows
user mode control of the FR bit (floating point register mode). It is
present if the UFRP bit is set in the floating point implementation
register.

This is a capability KVM may want to expose to guest kernels, even
though Linux is unlikely to ever use it due to the implications for
multi-threaded programs.

Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Acked-by: default avatarRalf Baechle <ralf@linux-mips.org>
Cc: Paul Burton <paul.burton@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
parent 97da3854

arch/mips/include/asm/cpu-features.h

+4 −0
Original line number Diff line number Diff line
@@ -444,6 +444,10 @@ 
# define cpu_has_msa		0

#endif



#ifndef cpu_has_ufr

# define cpu_has_ufr		(cpu_data[0].options & MIPS_CPU_UFR)

#endif



#ifndef cpu_has_fre

# define cpu_has_fre		(cpu_data[0].options & MIPS_CPU_FRE)

#endif

arch/mips/include/asm/cpu.h

+1 −0
Original line number Diff line number Diff line
@@ -415,6 +415,7 @@ enum cpu_type_enum { 
#define MIPS_CPU_GUESTCTL2	MBIT_ULL(50)	/* CPU has VZ GuestCtl2 register */

#define MIPS_CPU_GUESTID	MBIT_ULL(51)	/* CPU uses VZ ASE GuestID feature */

#define MIPS_CPU_DRG		MBIT_ULL(52)	/* CPU has VZ Direct Root to Guest (DRG) */

#define MIPS_CPU_UFR		MBIT_ULL(53)	/* CPU supports User mode FR switching */



/*

 * CPU ASE encodings

arch/mips/kernel/cpu-probe.c

+2 −0
Original line number Diff line number Diff line
@@ -289,6 +289,8 @@ static void cpu_set_fpu_opts(struct cpuinfo_mips *c) 
			    MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {

		if (c->fpu_id & MIPS_FPIR_3D)

			c->ases |= MIPS_ASE_MIPS3D;

		if (c->fpu_id & MIPS_FPIR_UFRP)

			c->options |= MIPS_CPU_UFR;

		if (c->fpu_id & MIPS_FPIR_FREP)

			c->options |= MIPS_CPU_FRE;

	}