Unverified Commit 4e729553 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
Browse files

!979 [sync] PR-943: Fixed the accelerator capability register issue. 

Merge Pull Request from: @xiao_jiang_shui 
 
Misc fixes for Kunpeng accelerator drivers!

Kai Ye (1):
  crypto: hisilicon/sec - misc cleanups

Wenkai Lin (3):
  crypto: hisilicon/sec - remove unused parameter
  crypto: hisilicon/sec - fix for resource leak
  crypto: hisilicon/qm - add a function to set qm algs

Zhiqi Song (4):
  crypto: hisilicon/qm - save capability registers in qm init process
  crypto: hisilicon/hpre - save capability registers in probe process
  crypto: hisilicon/sec2 - save capability registers in probe process 
 
Link:https://gitee.com/openeuler/kernel/pulls/979

 

Reviewed-by: default avatarYang Shen <shenyang39@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents 425ebf21 8356bfc1

drivers/crypto/hisilicon/hpre/hpre_main.c

+29 −39
Original line number Diff line number Diff line
@@ -117,8 +117,6 @@ 
#define HPRE_DFX_COMMON2_LEN		0xE

#define HPRE_DFX_CORE_LEN		0x43



#define HPRE_DEV_ALG_MAX_LEN	256



static const char hpre_name[] = "hisi_hpre";

static struct dentry *hpre_debugfs_root;

static const struct pci_device_id hpre_dev_ids[] = {
@@ -134,12 +132,7 @@ struct hpre_hw_error { 
	const char *msg;

};



struct hpre_dev_alg {

	u32 alg_msk;

	const char *alg;

};



static const struct hpre_dev_alg hpre_dev_algs[] = {

static const struct qm_dev_alg hpre_dev_algs[] = {

	{

		.alg_msk = BIT(0),

		.alg = "rsa\n"
@@ -232,6 +225,16 @@ static const struct hisi_qm_cap_info hpre_basic_info[] = { 
	{HPRE_CORE10_ALG_BITMAP_CAP, 0x3170, 0, GENMASK(31, 0), 0x0, 0x10, 0x10}

};



enum hpre_cap_reg_record_idx {

	HPRE_DRV_ALG_BITMAP_CAP_IDX,

	HPRE_DEV_ALG_BITMAP_CAP_IDX,

};



static struct hisi_qm_cap_record hpre_cap_reg_record[] = {

	{HPRE_DRV_ALG_BITMAP_CAP,	0x27},

	{HPRE_DEV_ALG_BITMAP_CAP,	0x7F},

};



static const struct hpre_hw_error hpre_hw_errors[] = {

	{

		.int_msk = BIT(0),
@@ -351,42 +354,13 @@ bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg) 
{

	u32 cap_val;



	cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DRV_ALG_BITMAP_CAP, qm->cap_ver);

	cap_val = hpre_cap_reg_record[HPRE_DRV_ALG_BITMAP_CAP_IDX].cap_val;

	if (alg & cap_val)

		return true;



	return false;

}



static int hpre_set_qm_algs(struct hisi_qm *qm)

{

	struct device *dev = &qm->pdev->dev;

	char *algs, *ptr;

	u32 alg_msk;

	int i;



	if (!qm->use_uacce)

		return 0;



	algs = devm_kzalloc(dev, HPRE_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL);

	if (!algs)

		return -ENOMEM;



	alg_msk = hisi_qm_get_hw_info(qm, hpre_basic_info, HPRE_DEV_ALG_BITMAP_CAP, qm->cap_ver);



	for (i = 0; i < ARRAY_SIZE(hpre_dev_algs); i++)

		if (alg_msk & hpre_dev_algs[i].alg_msk)

			strcat(algs, hpre_dev_algs[i].alg);



	ptr = strrchr(algs, '\n');

	if (ptr)

		*ptr = '\0';



	qm->uacce->algs = algs;



	return 0;

}



static int hpre_diff_regs_show(struct seq_file *s, void *unused)

{

	struct hisi_qm *qm = s->private;
@@ -1135,8 +1109,20 @@ static void hpre_debugfs_exit(struct hisi_qm *qm) 
	debugfs_remove_recursive(qm->debug.debug_root);

}



static void hpre_pre_store_cap_reg(struct hisi_qm *qm)

{

	int i, size;



	size = ARRAY_SIZE(hpre_cap_reg_record);

	for (i = 0; i < size; i++) {

		hpre_cap_reg_record[i].cap_val = hisi_qm_get_hw_info(qm, hpre_basic_info,

						 hpre_cap_reg_record[i].type, qm->cap_ver);

	}

}



static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)

{

	u64 alg_msk;

	int ret;



	if (pdev->revision == QM_HW_V1) {
@@ -1167,7 +1153,11 @@ static int hpre_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 
		return ret;

	}



	ret = hpre_set_qm_algs(qm);

	/* Fetch and save the value of capability registers */

	hpre_pre_store_cap_reg(qm);



	alg_msk = hpre_cap_reg_record[HPRE_DEV_ALG_BITMAP_CAP_IDX].cap_val;

	ret = hisi_qm_set_algs(qm, alg_msk, hpre_dev_algs, ARRAY_SIZE(hpre_dev_algs));

	if (ret) {

		pci_err(pdev, "Failed to set hpre algs!\n");

		hisi_qm_uninit(qm);

drivers/crypto/hisilicon/qm.c

+64 −8
Original line number Diff line number Diff line
@@ -226,6 +226,7 @@ 
#define QM_QOS_MIN_CIR_B		100

#define QM_QOS_MAX_CIR_U		6

#define QM_AUTOSUSPEND_DELAY		3000

#define QM_DEV_ALG_MAX_LEN		256



#define QM_MK_CQC_DW3_V1(hop_num, pg_sz, buf_sz, cqe_sz) \

	(((hop_num) << QM_CQ_HOP_NUM_SHIFT) | \
@@ -305,6 +306,13 @@ enum qm_basic_type { 
	QM_VF_IRQ_NUM_CAP,

};



enum qm_irq_type_caps_idx {

	QM_EQ_IRQ_TYPE_CAP_IDX,

	QM_AEQ_IRQ_TYPE_CAP_IDX,

	QM_ABN_IRQ_TYPE_CAP_IDX,

	QM_PF2VF_IRQ_TYPE_CAP_IDX

};



static const struct hisi_qm_cap_info qm_cap_info_comm[] = {

	{QM_SUPPORT_DB_ISOLATION, 0x30,   0, BIT(0),  0x0, 0x0, 0x0},

	{QM_SUPPORT_FUNC_QOS,     0x3100, 0, BIT(8),  0x0, 0x0, 0x1},
@@ -334,6 +342,13 @@ static const struct hisi_qm_cap_info qm_basic_info[] = { 
	{QM_VF_IRQ_NUM_CAP,     0x311c,   0,  GENMASK(15, 0), 0x1,       0x2,       0x3},

};



static struct hisi_qm_cap_record qm_irq_type_caps[] = {

	{QM_EQ_IRQ_TYPE_CAP,    0x10000},

	{QM_AEQ_IRQ_TYPE_CAP,   0x10001},

	{QM_ABN_IRQ_TYPE_CAP,   0x10003},

	{QM_PF2VF_IRQ_TYPE_CAP, 0x10002},

};



struct qm_mailbox {

	__le16 w0;

	__le16 queue_num;
@@ -781,6 +796,34 @@ static void qm_get_xqc_depth(struct hisi_qm *qm, u16 *low_bits, 
	*high_bits = (depth >> QM_XQ_DEPTH_SHIFT) & QM_XQ_DEPTH_MASK;

}



int hisi_qm_set_algs(struct hisi_qm *qm, u64 alg_msk, const struct qm_dev_alg *dev_algs,

		     u32 dev_algs_size)

{

	struct device *dev = &qm->pdev->dev;

	char *algs, *ptr;

	int i;



	if (!qm->use_uacce)

		return 0;



	algs = devm_kzalloc(dev, QM_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL);

	if (!algs)

		return -ENOMEM;



	for (i = 0; i < dev_algs_size; i++)

		if (alg_msk & dev_algs[i].alg_msk)

			strcat(algs, dev_algs[i].alg);



	ptr = strrchr(algs, '\n');

	if (ptr)

		*ptr = '\0';



	qm->uacce->algs = algs;



	return 0;

}

EXPORT_SYMBOL_GPL(hisi_qm_set_algs);



static u32 qm_get_irq_num(struct hisi_qm *qm)

{

	if (qm->fun_type == QM_HW_PF)
@@ -5073,7 +5116,7 @@ static void qm_unregister_abnormal_irq(struct hisi_qm *qm) 
	if (qm->fun_type == QM_HW_VF)

		return;



	val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_ABN_IRQ_TYPE_CAP, qm->cap_ver);

	val = qm_irq_type_caps[QM_ABN_IRQ_TYPE_CAP_IDX].cap_val;

	if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_ABN_IRQ_TYPE_MASK))

		return;
@@ -5090,7 +5133,7 @@ static int qm_register_abnormal_irq(struct hisi_qm *qm) 
	if (qm->fun_type == QM_HW_VF)

		return 0;



	val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_ABN_IRQ_TYPE_CAP, qm->cap_ver);

	val = qm_irq_type_caps[QM_ABN_IRQ_TYPE_CAP_IDX].cap_val;

	if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_ABN_IRQ_TYPE_MASK))

		return 0;
@@ -5107,7 +5150,7 @@ static void qm_unregister_mb_cmd_irq(struct hisi_qm *qm) 
	struct pci_dev *pdev = qm->pdev;

	u32 irq_vector, val;



	val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_PF2VF_IRQ_TYPE_CAP, qm->cap_ver);

	val = qm_irq_type_caps[QM_PF2VF_IRQ_TYPE_CAP_IDX].cap_val;

	if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))

		return;
@@ -5121,7 +5164,7 @@ static int qm_register_mb_cmd_irq(struct hisi_qm *qm) 
	u32 irq_vector, val;

	int ret;



	val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_PF2VF_IRQ_TYPE_CAP, qm->cap_ver);

	val = qm_irq_type_caps[QM_PF2VF_IRQ_TYPE_CAP_IDX].cap_val;

	if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))

		return 0;
@@ -5138,7 +5181,7 @@ static void qm_unregister_aeq_irq(struct hisi_qm *qm) 
	struct pci_dev *pdev = qm->pdev;

	u32 irq_vector, val;



	val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_AEQ_IRQ_TYPE_CAP, qm->cap_ver);

	val = qm_irq_type_caps[QM_AEQ_IRQ_TYPE_CAP_IDX].cap_val;

	if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))

		return;
@@ -5152,7 +5195,7 @@ static int qm_register_aeq_irq(struct hisi_qm *qm) 
	u32 irq_vector, val;

	int ret;



	val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_AEQ_IRQ_TYPE_CAP, qm->cap_ver);

	val = qm_irq_type_caps[QM_AEQ_IRQ_TYPE_CAP_IDX].cap_val;

	if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))

		return 0;
@@ -5170,7 +5213,7 @@ static void qm_unregister_eq_irq(struct hisi_qm *qm) 
	struct pci_dev *pdev = qm->pdev;

	u32 irq_vector, val;



	val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_EQ_IRQ_TYPE_CAP, qm->cap_ver);

	val = qm_irq_type_caps[QM_EQ_IRQ_TYPE_CAP_IDX].cap_val;

	if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))

		return;
@@ -5184,7 +5227,7 @@ static int qm_register_eq_irq(struct hisi_qm *qm) 
	u32 irq_vector, val;

	int ret;



	val = hisi_qm_get_hw_info(qm, qm_basic_info, QM_EQ_IRQ_TYPE_CAP, qm->cap_ver);

	val = qm_irq_type_caps[QM_EQ_IRQ_TYPE_CAP_IDX].cap_val;

	if (!((val >> QM_IRQ_TYPE_SHIFT) & QM_IRQ_TYPE_MASK))

		return 0;
@@ -5271,6 +5314,16 @@ static int qm_get_qp_num(struct hisi_qm *qm) 
	return 0;

}



static void qm_pre_store_irq_type_caps(struct hisi_qm *qm)

{

	int i, size;



	size = ARRAY_SIZE(qm_irq_type_caps);

	for (i = 0; i < size; i++)

		qm_irq_type_caps[i].cap_val = hisi_qm_get_hw_info(qm, qm_basic_info,

					      qm_irq_type_caps[i].type, qm->cap_ver);

}



static void qm_get_hw_caps(struct hisi_qm *qm)

{

	const struct hisi_qm_cap_info *cap_info = qm->fun_type == QM_HW_PF ?
@@ -5302,6 +5355,9 @@ static void qm_get_hw_caps(struct hisi_qm *qm) 
		if (val)

			set_bit(cap_info[i].type, &qm->caps);

	}



	/* Fetch and save the value of irq type related capability registers */

	qm_pre_store_irq_type_caps(qm);

}



static int qm_get_pci_res(struct hisi_qm *qm)

drivers/crypto/hisilicon/sec2/sec.h

+7 −0
Original line number Diff line number Diff line
@@ -219,6 +219,13 @@ enum sec_cap_type { 
	SEC_CORE4_ALG_BITMAP_HIGH,

};



enum sec_cap_reg_record_idx {

	SEC_DRV_ALG_BITMAP_LOW_IDX,

	SEC_DRV_ALG_BITMAP_HIGH_IDX,

	SEC_DEV_ALG_BITMAP_LOW_IDX,

	SEC_DEV_ALG_BITMAP_HIGH_IDX,

};



void sec_destroy_qps(struct hisi_qp **qps, int qp_num);

struct hisi_qp **sec_create_qps(void);

int sec_register_to_crypto(struct hisi_qm *qm);

drivers/crypto/hisilicon/sec2/sec_crypto.c

+42 −47
Original line number Diff line number Diff line
@@ -115,7 +115,7 @@ struct sec_aead { 
};



/* Get an en/de-cipher queue cyclically to balance load over queues of TFM */

static inline int sec_alloc_queue_id(struct sec_ctx *ctx, struct sec_req *req)

static inline u32 sec_alloc_queue_id(struct sec_ctx *ctx, struct sec_req *req)

{

	if (req->c_req.encrypt)

		return (u32)atomic_inc_return(&ctx->enc_qcyclic) %
@@ -482,8 +482,7 @@ static void sec_alg_resource_free(struct sec_ctx *ctx, 
		sec_free_mac_resource(dev, qp_ctx->res);

}



static int sec_alloc_qp_ctx_resource(struct hisi_qm *qm, struct sec_ctx *ctx,

				     struct sec_qp_ctx *qp_ctx)

static int sec_alloc_qp_ctx_resource(struct sec_ctx *ctx, struct sec_qp_ctx *qp_ctx)

{

	u16 q_depth = qp_ctx->qp->sq_depth;

	struct device *dev = ctx->dev;
@@ -538,8 +537,7 @@ static void sec_free_qp_ctx_resource(struct sec_ctx *ctx, struct sec_qp_ctx *qp_ 
	kfree(qp_ctx->req_list);

}



static int sec_create_qp_ctx(struct hisi_qm *qm, struct sec_ctx *ctx,

			     int qp_ctx_id, int alg_type)

static int sec_create_qp_ctx(struct sec_ctx *ctx, int qp_ctx_id)

{

	struct sec_qp_ctx *qp_ctx;

	struct hisi_qp *qp;
@@ -558,7 +556,7 @@ static int sec_create_qp_ctx(struct hisi_qm *qm, struct sec_ctx *ctx, 
	idr_init(&qp_ctx->req_idr);

	INIT_LIST_HEAD(&qp_ctx->backlog);



	ret = sec_alloc_qp_ctx_resource(qm, ctx, qp_ctx);

	ret = sec_alloc_qp_ctx_resource(ctx, qp_ctx);

	if (ret)

		goto err_destroy_idr;
@@ -611,7 +609,7 @@ static int sec_ctx_base_init(struct sec_ctx *ctx) 
	}



	for (i = 0; i < sec->ctx_q_num; i++) {

		ret = sec_create_qp_ctx(&sec->qm, ctx, i, 0);

		ret = sec_create_qp_ctx(ctx, i);

		if (ret)

			goto err_sec_release_qp_ctx;

	}
@@ -747,9 +745,7 @@ static void sec_skcipher_uninit(struct crypto_skcipher *tfm) 
	sec_ctx_base_uninit(ctx);

}



static int sec_skcipher_3des_setkey(struct crypto_skcipher *tfm, const u8 *key,

				    const u32 keylen,

				    const enum sec_cmode c_mode)

static int sec_skcipher_3des_setkey(struct crypto_skcipher *tfm, const u8 *key, const u32 keylen)

{

	struct sec_ctx *ctx = crypto_skcipher_ctx(tfm);

	struct sec_cipher_ctx *c_ctx = &ctx->c_ctx;
@@ -840,14 +836,12 @@ static int sec_skcipher_setkey(struct crypto_skcipher *tfm, const u8 *key, 


	switch (c_alg) {

	case SEC_CALG_3DES:

		ret = sec_skcipher_3des_setkey(tfm, key, keylen, c_mode);

		ret = sec_skcipher_3des_setkey(tfm, key, keylen);

		break;

	case SEC_CALG_AES:

	case SEC_CALG_SM4:

		ret = sec_skcipher_aes_sm4_setkey(c_ctx, keylen, c_mode);

		break;

	default:

		return -EINVAL;

	}



	if (ret) {
@@ -866,27 +860,6 @@ static int sec_skcipher_setkey(struct crypto_skcipher *tfm, const u8 *key, 
	return 0;

}



#define GEN_SEC_SETKEY_FUNC(name, c_alg, c_mode)			\

static int sec_setkey_##name(struct crypto_skcipher *tfm, const u8 *key,\

	u32 keylen)							\

{									\

	return sec_skcipher_setkey(tfm, key, keylen, c_alg, c_mode);	\

}



GEN_SEC_SETKEY_FUNC(aes_ecb, SEC_CALG_AES, SEC_CMODE_ECB)

GEN_SEC_SETKEY_FUNC(aes_cbc, SEC_CALG_AES, SEC_CMODE_CBC)

GEN_SEC_SETKEY_FUNC(aes_xts, SEC_CALG_AES, SEC_CMODE_XTS)

GEN_SEC_SETKEY_FUNC(aes_ofb, SEC_CALG_AES, SEC_CMODE_OFB)

GEN_SEC_SETKEY_FUNC(aes_cfb, SEC_CALG_AES, SEC_CMODE_CFB)

GEN_SEC_SETKEY_FUNC(aes_ctr, SEC_CALG_AES, SEC_CMODE_CTR)

GEN_SEC_SETKEY_FUNC(3des_ecb, SEC_CALG_3DES, SEC_CMODE_ECB)

GEN_SEC_SETKEY_FUNC(3des_cbc, SEC_CALG_3DES, SEC_CMODE_CBC)

GEN_SEC_SETKEY_FUNC(sm4_xts, SEC_CALG_SM4, SEC_CMODE_XTS)

GEN_SEC_SETKEY_FUNC(sm4_cbc, SEC_CALG_SM4, SEC_CMODE_CBC)

GEN_SEC_SETKEY_FUNC(sm4_ofb, SEC_CALG_SM4, SEC_CMODE_OFB)

GEN_SEC_SETKEY_FUNC(sm4_cfb, SEC_CALG_SM4, SEC_CMODE_CFB)

GEN_SEC_SETKEY_FUNC(sm4_ctr, SEC_CALG_SM4, SEC_CMODE_CTR)



static int sec_cipher_pbuf_map(struct sec_ctx *ctx, struct sec_req *req,

			struct scatterlist *src)

{
@@ -1011,6 +984,7 @@ static int sec_cipher_map(struct sec_ctx *ctx, struct sec_req *req, 
		ret = sec_aead_mac_init(a_req);

		if (unlikely(ret)) {

			dev_err(dev, "fail to init mac data for ICV!\n");

			hisi_acc_sg_buf_unmap(dev, src, req->in);

			return ret;

		}

	}
@@ -1368,7 +1342,7 @@ static int sec_skcipher_bd_fill_v3(struct sec_ctx *ctx, struct sec_req *req) 
	sec_sqe3->bd_param = cpu_to_le32(bd_param);



	sec_sqe3->c_len_ivin |= cpu_to_le32(c_req->c_len);

	sec_sqe3->tag = cpu_to_le64(req);

	sec_sqe3->tag = cpu_to_le64((unsigned long)(uintptr_t)req);



	return 0;

}
@@ -2093,7 +2067,7 @@ static int sec_skcipher_soft_crypto(struct sec_ctx *ctx, 


	skcipher_request_set_sync_tfm(subreq, c_ctx->fbtfm);



	/* software need sync mode to do crypto */

	/* Software need sync mode to do crypto */

	skcipher_request_set_callback(subreq, sreq->base.flags,

				      NULL, NULL);

	skcipher_request_set_crypt(subreq, sreq->src, sreq->dst,
@@ -2146,8 +2120,29 @@ static int sec_skcipher_decrypt(struct skcipher_request *sk_req) 
	return sec_skcipher_crypto(sk_req, false);

}



#define SEC_SKCIPHER_GEN_ALG(sec_cra_name, sec_set_key, sec_min_key_size, \

	sec_max_key_size, ctx_init, ctx_exit, blk_size, iv_size)\

#define GEN_SEC_SETKEY_FUNC(name, c_alg, c_mode)	                \

static int sec_setkey_##name(struct crypto_skcipher *tfm,	        \

	const u8 *key, u32 keylen)                                      \

{	                                                                \

	return sec_skcipher_setkey(tfm, key, keylen, c_alg, c_mode); \

}



GEN_SEC_SETKEY_FUNC(aes_ecb, SEC_CALG_AES, SEC_CMODE_ECB)

GEN_SEC_SETKEY_FUNC(aes_cbc, SEC_CALG_AES, SEC_CMODE_CBC)

GEN_SEC_SETKEY_FUNC(aes_xts, SEC_CALG_AES, SEC_CMODE_XTS)

GEN_SEC_SETKEY_FUNC(aes_ofb, SEC_CALG_AES, SEC_CMODE_OFB)

GEN_SEC_SETKEY_FUNC(aes_cfb, SEC_CALG_AES, SEC_CMODE_CFB)

GEN_SEC_SETKEY_FUNC(aes_ctr, SEC_CALG_AES, SEC_CMODE_CTR)

GEN_SEC_SETKEY_FUNC(3des_ecb, SEC_CALG_3DES, SEC_CMODE_ECB)

GEN_SEC_SETKEY_FUNC(3des_cbc, SEC_CALG_3DES, SEC_CMODE_CBC)

GEN_SEC_SETKEY_FUNC(sm4_xts, SEC_CALG_SM4, SEC_CMODE_XTS)

GEN_SEC_SETKEY_FUNC(sm4_cbc, SEC_CALG_SM4, SEC_CMODE_CBC)

GEN_SEC_SETKEY_FUNC(sm4_ofb, SEC_CALG_SM4, SEC_CMODE_OFB)

GEN_SEC_SETKEY_FUNC(sm4_cfb, SEC_CALG_SM4, SEC_CMODE_CFB)

GEN_SEC_SETKEY_FUNC(sm4_ctr, SEC_CALG_SM4, SEC_CMODE_CTR)



#define SEC_SKCIPHER_ALG(sec_cra_name, sec_set_key, \

	sec_min_key_size, sec_max_key_size, blk_size, iv_size)\

{\

	.base = {\

		.cra_name = sec_cra_name,\
@@ -2159,8 +2154,8 @@ static int sec_skcipher_decrypt(struct skcipher_request *sk_req) 
		.cra_ctxsize = sizeof(struct sec_ctx),\

		.cra_module = THIS_MODULE,\

	},\

	.init = ctx_init,\

	.exit = ctx_exit,\

	.init = sec_skcipher_ctx_init,\

	.exit = sec_skcipher_ctx_exit,\

	.setkey = sec_set_key,\

	.decrypt = sec_skcipher_decrypt,\

	.encrypt = sec_skcipher_encrypt,\
@@ -2169,11 +2164,6 @@ static int sec_skcipher_decrypt(struct skcipher_request *sk_req) 
	.ivsize = iv_size,\

}



#define SEC_SKCIPHER_ALG(name, key_func, min_key_size, \

	max_key_size, blk_size, iv_size) \

	SEC_SKCIPHER_GEN_ALG(name, key_func, min_key_size, max_key_size, \

	sec_skcipher_ctx_init, sec_skcipher_ctx_exit, blk_size, iv_size)



static struct sec_skcipher sec_skciphers[] = {

	{

		.alg_msk = BIT(0),
@@ -2545,9 +2535,11 @@ static int sec_register_aead(u64 alg_mask) 


int sec_register_to_crypto(struct hisi_qm *qm)

{

	u64 alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH, SEC_DRV_ALG_BITMAP_LOW);

	u64 alg_mask;

	int ret;



	alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH_IDX,

				      SEC_DRV_ALG_BITMAP_LOW_IDX);

	ret = sec_register_skcipher(alg_mask);

	if (ret)

		return ret;
@@ -2561,7 +2553,10 @@ int sec_register_to_crypto(struct hisi_qm *qm) 


void sec_unregister_from_crypto(struct hisi_qm *qm)

{

	u64 alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH, SEC_DRV_ALG_BITMAP_LOW);

	u64 alg_mask;



	alg_mask = sec_get_alg_bitmap(qm, SEC_DRV_ALG_BITMAP_HIGH_IDX,

				      SEC_DRV_ALG_BITMAP_LOW_IDX);



	sec_unregister_aead(alg_mask, ARRAY_SIZE(sec_aeads));

	sec_unregister_skcipher(alg_mask, ARRAY_SIZE(sec_skciphers));

drivers/crypto/hisilicon/sec2/sec_main.c

+49 −56
Original line number Diff line number Diff line
@@ -121,7 +121,6 @@ 
					GENMASK_ULL(42, 25))

#define SEC_AEAD_BITMAP			(GENMASK_ULL(7, 6) | GENMASK_ULL(18, 17) | \

					GENMASK_ULL(45, 43))

#define SEC_DEV_ALG_MAX_LEN		256



struct sec_hw_error {

	u32 int_msk;
@@ -133,11 +132,6 @@ struct sec_dfx_item { 
	u32 offset;

};



struct sec_dev_alg {

	u64 alg_msk;

	const char *algs;

};



static const char sec_name[] = "hisi_sec2";

static struct dentry *sec_debugfs_root;
@@ -174,74 +168,81 @@ static const struct hisi_qm_cap_info sec_basic_info[] = { 
	{SEC_CORE4_ALG_BITMAP_HIGH, 0x3170, 0, GENMASK(31, 0), 0x3FFF, 0x3FFF, 0x3FFF},

};



static const struct sec_dev_alg sec_dev_algs[] = { {

static struct hisi_qm_cap_record sec_cap_reg_record[] = {

	{SEC_DRV_ALG_BITMAP_LOW,	0x187F0FF},

	{SEC_DRV_ALG_BITMAP_HIGH,	0x395C},

	{SEC_DEV_ALG_BITMAP_LOW,	0xFFFFFFFF},

	{SEC_DEV_ALG_BITMAP_HIGH,	0x3FFF},

};



static const struct qm_dev_alg sec_dev_algs[] = { {

		.alg_msk = SEC_CIPHER_BITMAP,

		.algs = "cipher\n",

		.alg = "cipher\n",

	}, {

		.alg_msk = SEC_DIGEST_BITMAP,

		.algs = "digest\n",

		.alg = "digest\n",

	}, {

		.alg_msk = SEC_AEAD_BITMAP,

		.algs = "aead\n",

		.alg = "aead\n",

	},

};



static const struct sec_hw_error sec_hw_errors[] = {

	{

		.int_msk = BIT(0),

		.msg = "sec_axi_rresp_err_rint"

		.msg = "sec_axi_rresp_err_rint",

	},

	{

		.int_msk = BIT(1),

		.msg = "sec_axi_bresp_err_rint"

		.msg = "sec_axi_bresp_err_rint",

	},

	{

		.int_msk = BIT(2),

		.msg = "sec_ecc_2bit_err_rint"

		.msg = "sec_ecc_2bit_err_rint",

	},

	{

		.int_msk = BIT(3),

		.msg = "sec_ecc_1bit_err_rint"

		.msg = "sec_ecc_1bit_err_rint",

	},

	{

		.int_msk = BIT(4),

		.msg = "sec_req_trng_timeout_rint"

		.msg = "sec_req_trng_timeout_rint",

	},

	{

		.int_msk = BIT(5),

		.msg = "sec_fsm_hbeat_rint"

		.msg = "sec_fsm_hbeat_rint",

	},

	{

		.int_msk = BIT(6),

		.msg = "sec_channel_req_rng_timeout_rint"

		.msg = "sec_channel_req_rng_timeout_rint",

	},

	{

		.int_msk = BIT(7),

		.msg = "sec_bd_err_rint"

		.msg = "sec_bd_err_rint",

	},

	{

		.int_msk = BIT(8),

		.msg = "sec_chain_buff_err_rint"

		.msg = "sec_chain_buff_err_rint",

	},

	{

		.int_msk = BIT(14),

		.msg = "sec_no_secure_access"

		.msg = "sec_no_secure_access",

	},

	{

		.int_msk = BIT(15),

		.msg = "sec_wrapping_key_auth_err"

		.msg = "sec_wrapping_key_auth_err",

	},

	{

		.int_msk = BIT(16),

		.msg = "sec_km_key_crc_fail"

		.msg = "sec_km_key_crc_fail",

	},

	{

		.int_msk = BIT(17),

		.msg = "sec_axi_poison_err"

		.msg = "sec_axi_poison_err",

	},

	{

		.int_msk = BIT(18),

		.msg = "sec_sva_err"

		.msg = "sec_sva_err",

	},

	{}

};
@@ -282,6 +283,11 @@ static const struct debugfs_reg32 sec_dfx_regs[] = { 
	{"SEC_BD_SAA6                   ",  0x301C38},

	{"SEC_BD_SAA7                   ",  0x301C3C},

	{"SEC_BD_SAA8                   ",  0x301C40},

	{"SEC_RAS_CE_ENABLE             ",  0x301050},

	{"SEC_RAS_FE_ENABLE             ",  0x301054},

	{"SEC_RAS_NFE_ENABLE            ",  0x301058},

	{"SEC_REQ_TRNG_TIME_TH          ",  0x30112C},

	{"SEC_CHANNEL_RNG_REQ_THLD      ",  0x302110},

};



/* define the SEC's dfx regs region and region length */
@@ -395,8 +401,8 @@ u64 sec_get_alg_bitmap(struct hisi_qm *qm, u32 high, u32 low) 
{

	u32 cap_val_h, cap_val_l;



	cap_val_h = hisi_qm_get_hw_info(qm, sec_basic_info, high, qm->cap_ver);

	cap_val_l = hisi_qm_get_hw_info(qm, sec_basic_info, low, qm->cap_ver);

	cap_val_h = sec_cap_reg_record[high].cap_val;

	cap_val_l = sec_cap_reg_record[low].cap_val;



	return ((u64)cap_val_h << SEC_ALG_BITMAP_SHIFT) | (u64)cap_val_l;

}
@@ -1078,37 +1084,20 @@ static int sec_pf_probe_init(struct sec_dev *sec) 
	return ret;

}



static int sec_set_qm_algs(struct hisi_qm *qm)

static void sec_pre_store_cap_reg(struct hisi_qm *qm)

{

	struct device *dev = &qm->pdev->dev;

	char *algs, *ptr;

	u64 alg_mask;

	int i;

	int i, size;



	if (!qm->use_uacce)

		return 0;



	algs = devm_kzalloc(dev, SEC_DEV_ALG_MAX_LEN * sizeof(char), GFP_KERNEL);

	if (!algs)

		return -ENOMEM;



	alg_mask = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH, SEC_DEV_ALG_BITMAP_LOW);



	for (i = 0; i < ARRAY_SIZE(sec_dev_algs); i++)

		if (alg_mask & sec_dev_algs[i].alg_msk)

			strcat(algs, sec_dev_algs[i].algs);



	ptr = strrchr(algs, '\n');

	if (ptr)

		*ptr = '\0';



	qm->uacce->algs = algs;



	return 0;

	size = ARRAY_SIZE(sec_cap_reg_record);

	for (i = 0; i < size; i++) {

		sec_cap_reg_record[i].cap_val = hisi_qm_get_hw_info(qm, sec_basic_info,

						sec_cap_reg_record[i].type, qm->cap_ver);

	}

}



static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)

{

	u64 alg_msk;

	int ret;



	qm->pdev = pdev;
@@ -1143,7 +1132,11 @@ static int sec_qm_init(struct hisi_qm *qm, struct pci_dev *pdev) 
		return ret;

	}



	ret = sec_set_qm_algs(qm);

	/* Fetch and save the value of capability registers */

	sec_pre_store_cap_reg(qm);



	alg_msk = sec_get_alg_bitmap(qm, SEC_DEV_ALG_BITMAP_HIGH_IDX, SEC_DEV_ALG_BITMAP_LOW_IDX);

	ret = hisi_qm_set_algs(qm, alg_msk, sec_dev_algs, ARRAY_SIZE(sec_dev_algs));

	if (ret) {

		pci_err(qm->pdev, "Failed to set sec algs!\n");

		hisi_qm_uninit(qm);