Commit 4e5e2fd3 authored by tanghui20's avatar tanghui20 Committed by Xie XiuQi
Browse files

hpre:modify review coments of hpre driver 



driver inclusion
category:bugfix
bugzilla:NA
CVE:NA

modify review coments of hpre driver

Feature or Bugfix:Bugfix

Signed-off-by: default avatartanghui20 <tanghui20@huawei.com>
Reviewed-by: default avatarxuzaibo <xuzaibo@huawei.com>
Reviewed-by: default avatarZhou Wang <wangzhou1@hisilicon.com>
Reviewed-by: default avatarYang Yingliang <yangyingliang@huawei.com>
Signed-off-by: default avatarYang Yingliang <yangyingliang@huawei.com>
parent 2de0e279

drivers/crypto/hisilicon/hpre/hpre.h

+16 −35
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0+ */

/*

 * Copyright (c) 2018-2019 HiSilicon Limited.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 */

/* Copyright (c) 2019 HiSilicon Limited. */



#ifndef __HISI_HPRE_H

#define __HISI_HPRE_H
@@ -20,13 +12,10 @@ 
#define QM_CQ_SIZE			(QM_CQE_SIZE * QM_Q_DEPTH)

#define HPRE_PF_DEF_Q_NUM		64

#define HPRE_PF_DEF_Q_BASE		0

#define HPRE_RESET			0



struct hpre_ctrl;



enum hpre_status {

	HPRE_RESET,

};



struct hpre {

	struct hisi_qm qm;

	struct list_head list;
@@ -49,30 +38,22 @@ enum hpre_alg_type { 
};



struct hpre_sqe {

	__u32 alg	: 5;



	/* error type */

	__u32 etype	:11;

	__u32 resv0	: 14;

	__u32 done	: 2;

	__u32 task_len1	: 8;

	__u32 task_len2	: 8;

	__u32 mrttest_num	: 8;

	__u32 resv1	: 8;

	__u32 low_key;

	__u32 hi_key;

	__u32 low_in;

	__u32 hi_in;

	__u32 low_out;

	__u32 hi_out;

	__u32 tag	:16;

	__u32 resv2	:16;

	__le32 dw0;

	__u8 task_len1;

	__u8 task_len2;

	__u8 mrttest_num;

	__u8 resv1;

	__le64 key;

	__le64 in;

	__le64 out;

	__le16 tag;

	__le16 resv2;

#define _HPRE_SQE_ALIGN_EXT	7

	__u32 rsvd1[_HPRE_SQE_ALIGN_EXT];

	__le32 rsvd1[_HPRE_SQE_ALIGN_EXT];

};



extern struct hpre *find_hpre_device(int node);

extern int hpre_algs_register(void);

extern void hpre_algs_unregister(void);

struct hpre *find_hpre_device(int node);

int hpre_algs_register(void);

void hpre_algs_unregister(void);



#endif

drivers/crypto/hisilicon/hpre/hpre_crypto.c

+203 −197
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0+

/*

 * Copyright (c) 2018-2019 HiSilicon Limited.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 *

 */

/* Copyright (c) 2019 HiSilicon Limited. */



#include <linux/module.h>

#include <crypto/internal/rsa.h>

#include <crypto/internal/akcipher.h>

#include <crypto/akcipher.h>

#include <crypto/kpp.h>

#include <crypto/internal/kpp.h>

#include <crypto/dh.h>

#include <crypto/scatterwalk.h>

#include <linux/module.h>

#include <linux/dma-mapping.h>

#include <linux/fips.h>

#include <crypto/scatterwalk.h>



#include "hpre.h"
@@ -28,20 +20,21 @@ struct hpre_ctx; 
#define HPRE_ALIGN_SZ		64

#define HPRE_BITS_2_BYTES_SHIFT	3

#define HPRE_RSA_INVLD_KEY_SZ	64

#define _CRT_PRMS		5

#define _CRT_Q			2

#define _CRT_P			3

#define _CRT_INV			4

#define _DH_G_FLAG		0x02

#define HPRE_CRT_PRMS		5

#define HPRE_CRT_Q			2

#define HPRE_CRT_P			3

#define HPRE_CRT_INV			4

#define HPRE_DH_G_FLAG		0x02

#define HPRE_TRY_SEND_TIMES	100

#define HPRE_INVLD_REQ_ID		(-1)

#define GET_DEV(ctx)		((ctx)->qp->qm->pdev->dev)

#define HPRE_DEV(ctx)		((ctx)->qp->qm->pdev->dev)



#define HPRE_SQE_ALG_BITS	5

#define HPRE_SQE_DONE_SHIFT	30



#define BITS64_MERGE(low_32, high_32)	(((u64)(low_32)) | \

					(((u64)(high_32)) << 32))

typedef void (*hpre_cb)(struct hpre_ctx *ctx, void *sqe);



struct _rsa_ctx {

struct hpre_rsa_ctx {

	/* low address: e--->n */

	char *pubkey;
@@ -56,7 +49,7 @@ struct _rsa_ctx { 
	struct crypto_akcipher *soft_tfm;

};



struct _dh_ctx {

struct hpre_dh_ctx {

	/*

	 * If base is g we compute the public key

	 *	ya = g^xa mod p; [RFC2631 sec 2.1.1]
@@ -64,7 +57,7 @@ struct _dh_ctx { 
	 * compute the shared secret

	 *	ZZ = yb^xa mod p; [RFC2631 sec 2.1.1]

	 */

	char *xa_p; /* low address: d--->n */

	char *xa_p; /* low address: d--->n, please refer to Hisilicon HPRE UM */

	char *g; /* m */

	dma_addr_t dma_xa_p;

	dma_addr_t dma_g;
@@ -78,8 +71,8 @@ struct hpre_ctx { 
	unsigned int key_sz;

	bool crt_g2_mode;

	union {

		struct _rsa_ctx rsa;

		struct _dh_ctx dh;

		struct hpre_rsa_ctx rsa;

		struct hpre_dh_ctx dh;

	};

};
@@ -97,7 +90,8 @@ struct hpre_asym_request { 
	hpre_cb cb;

};



static void _rsa_cb(struct hpre_ctx *ctx, void *resp);

static DEFINE_MUTEX(hpre_alg_lock);

static unsigned int hpre_active_devs;



static int hpre_alloc_req_id(struct hpre_ctx *ctx)

{
@@ -108,7 +102,7 @@ static int hpre_alloc_req_id(struct hpre_ctx *ctx) 
	id = find_first_zero_bit(ctx->req_bitmap, QM_Q_DEPTH);

	if (id >= QM_Q_DEPTH) {

		spin_unlock_irqrestore(&ctx->req_lock, flags);

		pr_err("nno free req id!\n");

		pr_err("no free req id in hpre context!\n");

		return -EBUSY;

	}

	set_bit(id, ctx->req_bitmap);
@@ -156,21 +150,23 @@ static void hpre_rm_req_from_ctx(struct hpre_asym_request *hpre_req) 


static struct hisi_qp *hpre_get_qp(void)

{

	struct hisi_qp *qp = NULL;

	struct hisi_qp *qp;

	struct hpre *hpre;

	int ret;



	/* find the proper hpre device */

	/* find the proper hpre device, which is near the current CPU core */

	hpre = find_hpre_device(cpu_to_node(smp_processor_id()));

	if (!hpre) {

		pr_err("Can not find proper hpre device!\n");

		return ERR_PTR(-ENODEV);

	}



	qp = hisi_qm_create_qp(&hpre->qm, 0);

	if (IS_ERR(qp)) {

		dev_err(&hpre->qm.pdev->dev, "Can not create qp!\n");

		return ERR_PTR(-ENODEV);

	}



	ret = hisi_qm_start_qp(qp, 0);

	if (ret < 0) {

		hisi_qm_release_qp(qp);
@@ -181,13 +177,13 @@ static struct hisi_qp *hpre_get_qp(void) 
	return qp;

}



static int _get_data_dma_addr(struct hpre_asym_request *hpre_req,

static int hpre_get_data_dma_addr(struct hpre_asym_request *hpre_req,

			      struct scatterlist *data, unsigned int len,

			      int is_src, dma_addr_t *tmp)

{

	enum dma_data_direction dma_dir;

	struct hpre_ctx *ctx = hpre_req->ctx;

	struct device *dev = &GET_DEV(ctx);

	struct device *dev = &HPRE_DEV(ctx);



	if (is_src) {

		hpre_req->src_align = NULL;
@@ -198,7 +194,7 @@ static int _get_data_dma_addr(struct hpre_asym_request *hpre_req, 
	}

	*tmp = dma_map_single(dev, sg_virt(data),

			      len, dma_dir);

	if (unlikely(dma_mapping_error(dev, *tmp))) {

	if (dma_mapping_error(dev, *tmp)) {

		dev_err(dev, "dma map data err!\n");

		return -ENOMEM;

	}
@@ -206,12 +202,12 @@ static int _get_data_dma_addr(struct hpre_asym_request *hpre_req, 
	return 0;

}



static int _cp_data_to_dma_buf(struct hpre_asym_request *hpre_req,

static int hpre_prepare_dma_buf(struct hpre_asym_request *hpre_req,

			       struct scatterlist *data, unsigned int len,

			       int is_src, dma_addr_t *tmp)

{

	struct hpre_ctx *ctx = hpre_req->ctx;

	struct device *dev = &GET_DEV(ctx);

	struct device *dev = &HPRE_DEV(ctx);

	char *ptr;

	int shift;
@@ -220,10 +216,10 @@ static int _cp_data_to_dma_buf(struct hpre_asym_request *hpre_req, 
		return -EINVAL;



	ptr = dma_alloc_coherent(dev, ctx->key_sz, tmp, GFP_KERNEL);

	if (unlikely(!ptr)) {

		dev_err(dev, "dma alloc data err!\n");

	if (!ptr) {

		return -ENOMEM;

	}



	if (is_src) {

		scatterwalk_map_and_copy(ptr + shift, data, 0, len, 0);

		hpre_req->src_align = ptr;
@@ -234,7 +230,7 @@ static int _cp_data_to_dma_buf(struct hpre_asym_request *hpre_req, 
	return 0;

}



static int _hw_data_init(struct hpre_asym_request *hpre_req,

static int hpre_hw_data_init(struct hpre_asym_request *hpre_req,

			 struct scatterlist *data, unsigned int len,

			 int is_src, int is_dh)

{
@@ -246,36 +242,36 @@ static int _hw_data_init(struct hpre_asym_request *hpre_req, 
	/* when the data is dh's source, we should format it */

	if ((sg_is_last(data) && len == ctx->key_sz) &&

	    ((is_dh && !is_src) || !is_dh)) {

		ret = _get_data_dma_addr(hpre_req, data, len, is_src, &tmp);

		ret = hpre_get_data_dma_addr(hpre_req, data, len, is_src, &tmp);

		if (ret)

			return ret;

	} else {

		ret = _cp_data_to_dma_buf(hpre_req, data, len,

		ret = hpre_prepare_dma_buf(hpre_req, data, len,

					  is_src, &tmp);

		if (ret)

			return ret;

	}

	if (is_src) {

		msg->low_in = lower_32_bits(tmp);

		msg->hi_in = upper_32_bits(tmp);

	} else {

		msg->low_out = lower_32_bits(tmp);

		msg->hi_out = upper_32_bits(tmp);

	}

	if (is_src)

		msg->in = cpu_to_le64(tmp);

	else

		msg->out = cpu_to_le64(tmp);



	return 0;

}



static void _hw_data_clr_all(struct hpre_ctx *ctx,

static void hpre_hw_data_clr_all(struct hpre_ctx *ctx,

			     struct hpre_asym_request *req,

			     struct scatterlist *dst, struct scatterlist *src)

{

	dma_addr_t tmp;

	struct device *dev = &GET_DEV(ctx);

	struct device *dev = &HPRE_DEV(ctx);

	struct hpre_sqe *sqe = &req->req;



	tmp = BITS64_MERGE(sqe->low_in, sqe->hi_in);

	if (src && tmp) {

	tmp = le64_to_cpu(sqe->in);

	if (!tmp)

		return;



	if (src) {

		if (req->src_align)

			dma_free_coherent(dev, ctx->key_sz,

					  req->src_align, tmp);
@@ -283,37 +279,45 @@ static void _hw_data_clr_all(struct hpre_ctx *ctx, 
			dma_unmap_single(dev, tmp,

					 ctx->key_sz, DMA_TO_DEVICE);

	}

	tmp = BITS64_MERGE(sqe->low_out, sqe->hi_out);

	if (req->dst_align && tmp) {



	tmp = le64_to_cpu(sqe->out);

	if (!tmp)

		return;



	if (req->dst_align) {

		if (dst)

			scatterwalk_map_and_copy(req->dst_align, dst, 0,

						 ctx->key_sz, 1);

		dma_free_coherent(dev, ctx->key_sz, req->dst_align, tmp);

	} else if (!req->dst_align && tmp) {

	} else

		dma_unmap_single(dev, tmp, ctx->key_sz, DMA_FROM_DEVICE);

}

}



static int _alg_res_post_hf(struct hpre_ctx *ctx, struct hpre_sqe *sqe,

static int hpre_alg_res_post_hf(struct hpre_ctx *ctx, struct hpre_sqe *sqe,

			    void **kreq)

{

	struct hpre_asym_request *req;

	int err, id;

	int err, id, done;



#define HPRE_NO_HW_ERR		0

#define HPRE_HW_TASK_DONE	3

	id = (int)sqe->tag;

#define HREE_HW_ERR_MASK	0x7ff

#define HREE_SQE_DONE_MASK	0x3

	id = (int)le16_to_cpu(sqe->tag);

	req = ctx->req_list[id];

	hpre_rm_req_from_ctx(req);

	*kreq = req;

	err = sqe->etype;

	err = (err == HPRE_NO_HW_ERR && sqe->done ==

		HPRE_HW_TASK_DONE) ? 0 : -EINVAL;

	err = (le32_to_cpu(sqe->dw0) >> HPRE_SQE_ALG_BITS) &

		HREE_HW_ERR_MASK;

	done = (le32_to_cpu(sqe->dw0) >> HPRE_SQE_DONE_SHIFT) &

		HREE_SQE_DONE_MASK;

	err = (err == HPRE_NO_HW_ERR &&

		done == HPRE_HW_TASK_DONE) ? 0 : -EINVAL;



	return err;

}



static int _ctx_init(struct hpre_ctx *ctx, struct hisi_qp *qp, int qlen)

static int hpre_ctx_set(struct hpre_ctx *ctx, struct hisi_qp *qp, int qlen)

{

	if (!ctx || !qp || qlen < 0)

		return -EINVAL;
@@ -335,7 +339,7 @@ static int _ctx_init(struct hpre_ctx *ctx, struct hisi_qp *qp, int qlen) 
	return 0;

}



static void _ctx_clear(struct hpre_ctx *ctx, bool is_exit)

static void hpre_ctx_clear(struct hpre_ctx *ctx, bool is_exit)

{

	if (is_exit) {

		kfree(ctx->req_bitmap);
@@ -347,28 +351,38 @@ static void _ctx_clear(struct hpre_ctx *ctx, bool is_exit) 
	ctx->key_sz = 0;

}



static void _dh_cb(struct hpre_ctx *ctx, void *resp)

static void hpre_dh_cb(struct hpre_ctx *ctx, void *resp)

{

	struct kpp_request *areq;

	struct hpre_asym_request *req;

	int ret;



	ret = _alg_res_post_hf(ctx, resp, (void **)&req);

	ret = hpre_alg_res_post_hf(ctx, resp, (void **)&req);

	areq = req->areq.dh;

	areq->dst_len = ctx->key_sz;

	_hw_data_clr_all(ctx, req, areq->dst, areq->src);

	hpre_hw_data_clr_all(ctx, req, areq->dst, areq->src);

	kpp_request_complete(areq, ret);

}



static void hpre_rsa_cb(struct hpre_ctx *ctx, void *resp)

{

	struct hpre_asym_request *req;

	struct akcipher_request *areq;

	int ret;



	ret = hpre_alg_res_post_hf(ctx, resp, (void **)&req);

	areq = req->areq.rsa;

	areq->dst_len = ctx->key_sz;

	hpre_hw_data_clr_all(ctx, req, areq->dst, areq->src);

	akcipher_request_complete(areq, ret);

}



static void hpre_alg_cb(struct hisi_qp *qp, void *_resp)

{

	struct hpre_sqe *sqe = _resp;

	struct hpre_asym_request *areq;

	struct hpre_ctx *ctx = qp->qp_ctx;

	u32 id = sqe->tag;



	areq = ctx->req_list[id];

	areq->cb(ctx, _resp);

	ctx->req_list[sqe->tag]->cb(ctx, _resp);

}



static int hpre_ctx_init(struct hpre_ctx *ctx)
@@ -381,7 +395,7 @@ static int hpre_ctx_init(struct hpre_ctx *ctx) 
	qp->qp_ctx = ctx;

	qp->req_cb = hpre_alg_cb;



	return _ctx_init(ctx, qp, QM_Q_DEPTH);

	return hpre_ctx_set(ctx, qp, QM_Q_DEPTH);

}



static int hpre_msg_comm_set(struct hpre_ctx *ctx, void *req, bool is_rsa)
@@ -402,10 +416,10 @@ static int hpre_msg_comm_set(struct hpre_ctx *ctx, void *req, bool is_rsa) 
		}

		tmp = akcipher_request_ctx(akreq);

		h_req = PTR_ALIGN(tmp, HPRE_ALIGN_SZ);

		h_req->cb = _rsa_cb;

		h_req->cb = hpre_rsa_cb;

		h_req->areq.rsa = akreq;

		msg = &h_req->req;

		memset(msg, '\0', sizeof(*msg));

		memset(msg, 0, sizeof(*msg));

	} else {

		struct kpp_request *kreq = req;
@@ -415,20 +429,20 @@ static int hpre_msg_comm_set(struct hpre_ctx *ctx, void *req, bool is_rsa) 
		}

		tmp = kpp_request_ctx(kreq);

		h_req = PTR_ALIGN(tmp, HPRE_ALIGN_SZ);

		h_req->cb = _dh_cb;

		h_req->cb = hpre_dh_cb;

		h_req->areq.dh = kreq;

		msg = &h_req->req;

		memset(msg, '\0', sizeof(*msg));

		msg->low_key = lower_32_bits(ctx->dh.dma_xa_p);

		msg->hi_key = upper_32_bits(ctx->dh.dma_xa_p);

		memset(msg, 0, sizeof(*msg));

		msg->key = cpu_to_le64((u64)ctx->dh.dma_xa_p);

	}

	msg->done = 1;



	msg->dw0 |= cpu_to_le32(0x1 << HPRE_SQE_DONE_SHIFT);

	msg->task_len1 = (ctx->key_sz >> HPRE_BITS_2_BYTES_SHIFT) - 1;

	h_req->ctx = ctx;

	req_id = hpre_add_req_to_ctx(h_req);

	if (req_id < 0)

		return -EBUSY;

	msg->tag = (u16)req_id;

	msg->tag = cpu_to_le16((u16)req_id);



	return 0;

}
@@ -448,26 +462,27 @@ static int hpre_dh_compute_value(struct kpp_request *req) 
	if (ret)

		return ret;

	if (req->src) {

		ret = _hw_data_init(hpre_req, req->src, req->src_len, 1, 1);

		ret = hpre_hw_data_init(hpre_req, req->src, req->src_len, 1, 1);

		if (ret)

			goto clear_all;

	}

	ret = _hw_data_init(hpre_req, req->dst, req->dst_len, 0, 1);

	ret = hpre_hw_data_init(hpre_req, req->dst, req->dst_len, 0, 1);

	if (ret)

		goto clear_all;

	if (ctx->crt_g2_mode && !req->src)

		msg->alg = HPRE_ALG_DH_G2;

		msg->dw0 |= HPRE_ALG_DH_G2;

	else

		msg->alg = HPRE_ALG_DH;

		msg->dw0 |= HPRE_ALG_DH;

	do {

		ret = hisi_qp_send(ctx->qp, msg);

	} while (ret == -EBUSY && ctr++ < HPRE_TRY_SEND_TIMES);



	/* success */

	if (!ret)

		return -EINPROGRESS;

clear_all:

	hpre_rm_req_from_ctx(hpre_req);

	_hw_data_clr_all(ctx, hpre_req, req->dst, req->src);

	hpre_hw_data_clr_all(ctx, hpre_req, req->dst, req->src);

	return ret;

}
@@ -494,7 +509,7 @@ static int hpre_dh_check_params_length(unsigned int key_sz) 


static int hpre_dh_set_params(struct hpre_ctx *ctx, struct dh *params)

{

	struct device *dev = &GET_DEV(ctx);

	struct device *dev = &HPRE_DEV(ctx);

	unsigned int sz;



#define _HPRE_DH_MAX_P_SZ	512
@@ -513,7 +528,7 @@ static int hpre_dh_set_params(struct hpre_ctx *ctx, struct dh *params) 
	memcpy(ctx->dh.xa_p + sz, params->p, sz);



	/* If g equals 2 don't copy it */

	if (params->g_size == 1 && *(char *)params->g == _DH_G_FLAG) {

	if (params->g_size == 1 && *(char *)params->g == HPRE_DH_G_FLAG) {

		ctx->crt_g2_mode = true;

		return 0;

	}
@@ -526,8 +541,7 @@ static int hpre_dh_set_params(struct hpre_ctx *ctx, struct dh *params) 
		return -ENOMEM;

	}



	memcpy(ctx->dh.g + (sz - params->g_size), params->g,

	       params->g_size);

	memcpy(ctx->dh.g + (sz - params->g_size), params->g, params->g_size);



	return 0;

}
@@ -535,21 +549,23 @@ static int hpre_dh_set_params(struct hpre_ctx *ctx, struct dh *params) 
static void hpre_dh_clear_ctx(struct hpre_ctx *ctx, bool is_exit)

{

	unsigned int sz = ctx->key_sz;

	struct device *dev = &GET_DEV(ctx);

	struct device *dev = &HPRE_DEV(ctx);



	if (is_exit)

		hisi_qm_stop_qp(ctx->qp);



	if (ctx->dh.g) {

		memset(ctx->dh.g, 0, sz);

		dma_free_coherent(dev, sz, ctx->dh.g, ctx->dh.dma_g);

		ctx->dh.g = NULL;

	}

	if (ctx->dh.xa_p) {

		memset(ctx->dh.xa_p, 0, sz);

		dma_free_coherent(dev, sz << 1, ctx->dh.xa_p,

				ctx->dh.dma_xa_p);

		ctx->dh.xa_p = NULL;

	}

	_ctx_clear(ctx, is_exit);

	hpre_ctx_clear(ctx, is_exit);

}



static int hpre_dh_set_secret(struct crypto_kpp *tfm, const void *buf,
@@ -601,22 +617,17 @@ static void hpre_dh_exit_tfm(struct crypto_kpp *tfm) 
}

#endif



static void _rsa_cb(struct hpre_ctx *ctx, void *resp)

static void hpre_rsa_drop_leading_zeros(const char **ptr, size_t *len)

{

	struct akcipher_request *areq;

	struct hpre_asym_request *req;

	int ret;



	ret = _alg_res_post_hf(ctx, resp, (void **)&req);

	areq = req->areq.rsa;

	areq->dst_len = ctx->key_sz;

	_hw_data_clr_all(ctx, req, areq->dst, areq->src);

	akcipher_request_complete(areq, ret);

	while (!**ptr && *len) {

		(*ptr)++;

		(*len)--;

	}

}



static int hpre_rsa_key_size_check(unsigned int len)

static bool hpre_rsa_key_size_is_valid(unsigned int len)

{

	unsigned int bitslen = len << HPRE_BITS_2_BYTES_SHIFT;

	unsigned int bits = len << HPRE_BITS_2_BYTES_SHIFT;



#define _RSA_512BITS_KEY_WDTH		512

#define _RSA_1024BITS_KEY_WDTH		1024
@@ -624,16 +635,16 @@ static int hpre_rsa_key_size_check(unsigned int len) 
#define _RSA_3072BITS_KEY_WDTH		3072

#define _RSA_4096BITS_KEY_WDTH		4096



	switch (bitslen) {

	switch (bits) {

	/* 512bits is not supported by HPRE now! */

	case _RSA_512BITS_KEY_WDTH:

	case _RSA_1024BITS_KEY_WDTH:

	case _RSA_2048BITS_KEY_WDTH:

	case _RSA_3072BITS_KEY_WDTH:

	case _RSA_4096BITS_KEY_WDTH:

		return 0;

		return true;

	default:

		return -EINVAL;

		return false;

	}

}
@@ -655,29 +666,35 @@ static int hpre_rsa_enc(struct akcipher_request *req) 
		akcipher_request_set_tfm(req, tfm);

		return ret;

	}

	if (unlikely(!ctx->rsa.pubkey))



	if (!ctx->rsa.pubkey)

		return -EINVAL;



	ret = hpre_msg_comm_set(ctx, req, 1);

	if (ret)

		return ret;

	msg->alg = HPRE_ALG_NC_NCRT;

	msg->low_key = lower_32_bits(ctx->rsa.dma_pubkey);

	msg->hi_key = upper_32_bits(ctx->rsa.dma_pubkey);

	ret = _hw_data_init(hpre_req, req->src, req->src_len, 1, 0);



	msg->dw0 |= HPRE_ALG_NC_NCRT;

	msg->key = cpu_to_le64((u64)ctx->rsa.dma_pubkey);



	ret = hpre_hw_data_init(hpre_req, req->src, req->src_len, 1, 0);

	if (ret)

		goto clear_all;

	ret = _hw_data_init(hpre_req, req->dst, req->dst_len, 0, 0);



	ret = hpre_hw_data_init(hpre_req, req->dst, req->dst_len, 0, 0);

	if (ret)

		goto clear_all;



	do {

		ret = hisi_qp_send(ctx->qp, msg);

	} while (ret == -EBUSY && ctr++ < HPRE_TRY_SEND_TIMES);



	/* success */

	if (!ret)

		return -EINPROGRESS;

clear_all:

	hpre_rm_req_from_ctx(hpre_req);

	_hw_data_clr_all(ctx, hpre_req, req->dst, req->src);

	hpre_hw_data_clr_all(ctx, hpre_req, req->dst, req->src);



	return ret;

}
@@ -700,26 +717,27 @@ static int hpre_rsa_dec(struct akcipher_request *req) 
		akcipher_request_set_tfm(req, tfm);

		return ret;

	}

	if (unlikely(!ctx->rsa.prikey))



	if (!ctx->rsa.prikey)

		return -EINVAL;



	ret = hpre_msg_comm_set(ctx, req, 1);

	if (ret)

		return ret;



	if (ctx->crt_g2_mode) {

		msg->low_key = lower_32_bits(ctx->rsa.dma_crt_prikey);

		msg->hi_key = upper_32_bits(ctx->rsa.dma_crt_prikey);

		msg->alg = HPRE_ALG_NC_CRT;

		msg->key = cpu_to_le64((u64)ctx->rsa.dma_crt_prikey);

		msg->dw0 |= HPRE_ALG_NC_CRT;

	} else {

		msg->low_key = lower_32_bits(ctx->rsa.dma_prikey);

		msg->hi_key = upper_32_bits(ctx->rsa.dma_prikey);

		msg->alg = HPRE_ALG_NC_NCRT;

		msg->key = cpu_to_le64((u64)ctx->rsa.dma_prikey);

		msg->dw0 |= HPRE_ALG_NC_NCRT;

	}



	ret = _hw_data_init(hpre_req, req->src, req->src_len, 1, 0);

	ret = hpre_hw_data_init(hpre_req, req->src, req->src_len, 1, 0);

	if (ret)

		goto clear_all;

	ret = _hw_data_init(hpre_req, req->dst, req->dst_len, 0, 0);



	ret = hpre_hw_data_init(hpre_req, req->dst, req->dst_len, 0, 0);

	if (ret)

		goto clear_all;
@@ -727,11 +745,12 @@ static int hpre_rsa_dec(struct akcipher_request *req) 
		ret = hisi_qp_send(ctx->qp, msg);

	} while (ret == -EBUSY && ctr++ < HPRE_TRY_SEND_TIMES);



	/* success */

	if (!ret)

		return -EINPROGRESS;

clear_all:

	hpre_rm_req_from_ctx(hpre_req);

	_hw_data_clr_all(ctx, hpre_req, req->dst, req->src);

	hpre_hw_data_clr_all(ctx, hpre_req, req->dst, req->src);



	return ret;

}
@@ -741,38 +760,35 @@ static int hpre_rsa_set_n(struct hpre_ctx *ctx, const char *value, 
{

	const char *ptr = value;



	while (!*ptr && vlen) {

		ptr++;

		vlen--;

	}

	hpre_rsa_drop_leading_zeros(&ptr, &vlen);



	ctx->key_sz = vlen;



	/* invalid key size provided */

	if (hpre_rsa_key_size_check(ctx->key_sz)) {

	/* if invalid key size provided */

	if (!hpre_rsa_key_size_is_valid(ctx->key_sz)) {

		ctx->key_sz = 0;

		return -EINVAL;

	}



	if (private) {

		ctx->rsa.prikey = dma_alloc_coherent(&GET_DEV(ctx), vlen << 1,

		ctx->rsa.prikey = dma_alloc_coherent(&HPRE_DEV(ctx), vlen << 1,

						     &ctx->rsa.dma_prikey,

						     GFP_KERNEL);

		if (!ctx->rsa.prikey)

			return -ENOMEM;

	}



	ctx->rsa.pubkey = dma_alloc_coherent(&GET_DEV(ctx), vlen << 1,

	ctx->rsa.pubkey = dma_alloc_coherent(&HPRE_DEV(ctx), vlen << 1,

					     &ctx->rsa.dma_pubkey,

					     GFP_KERNEL);

	if (!ctx->rsa.pubkey) {

		if (ctx->rsa.prikey) {

			dma_free_coherent(&GET_DEV(ctx), vlen << 1,

			dma_free_coherent(&HPRE_DEV(ctx), vlen << 1,

					ctx->rsa.prikey, ctx->rsa.dma_prikey);

			ctx->rsa.prikey = NULL;

		}

		return -ENOMEM;

	}



	memcpy(ctx->rsa.pubkey + vlen, ptr, vlen);

	if (ctx->rsa.prikey)

		memcpy(ctx->rsa.prikey + vlen, ptr, vlen);
@@ -785,12 +801,12 @@ static int hpre_rsa_set_e(struct hpre_ctx *ctx, const char *value, 
{

	const char *ptr = value;



	while (!*ptr && vlen) {

		ptr++;

		vlen--;

	}

	if (!ctx->key_sz || !vlen || vlen > ctx->key_sz)

	hpre_rsa_drop_leading_zeros(&ptr, &vlen);



	if (!ctx->key_sz || !vlen || vlen > ctx->key_sz) {

		ctx->rsa.pubkey = NULL;

		return -EINVAL;

	}



	memcpy(ctx->rsa.pubkey + ctx->key_sz - vlen, ptr, vlen);
@@ -802,10 +818,8 @@ static int hpre_rsa_set_d(struct hpre_ctx *ctx, const char *value, 
{

	const char *ptr = value;



	while (!*ptr && vlen) {

		ptr++;

		vlen--;

	}

	hpre_rsa_drop_leading_zeros(&ptr, &vlen);



	if (!ctx->key_sz || !vlen || vlen > ctx->key_sz)

		return -EINVAL;
@@ -813,19 +827,11 @@ static int hpre_rsa_set_d(struct hpre_ctx *ctx, const char *value, 
	return 0;

}



static void hpre_rsa_drop_leading_zeros(const char **ptr, unsigned int *len)

{

	while (!**ptr && *len) {

		(*ptr)++;

		(*len)--;

	}

}



static int hpre_crt_para_get(char *para, const char *raw,

			     unsigned int raw_sz, unsigned int para_size)

{

	const char *ptr = raw;

	unsigned int len = raw_sz;

	size_t len = raw_sz;



	hpre_rsa_drop_leading_zeros(&ptr, &len);

	if (!len)
@@ -837,56 +843,53 @@ static int hpre_crt_para_get(char *para, const char *raw, 
}

static int hpre_rsa_setkey_crt(struct hpre_ctx *ctx, struct rsa_key *rsa_key)

{

	struct device *dev = &GET_DEV(ctx);

	struct device *dev = &HPRE_DEV(ctx);

	unsigned int hlf_ksz = ctx->key_sz >> 1;

	int ret;

	u64 offset;



	ctx->rsa.crt_prikey = dma_alloc_coherent(dev, hlf_ksz * _CRT_PRMS,

	ctx->rsa.crt_prikey = dma_alloc_coherent(dev, hlf_ksz * HPRE_CRT_PRMS,

					&ctx->rsa.dma_crt_prikey,

					GFP_KERNEL);

	if (!ctx->rsa.crt_prikey)

		return -ENOMEM;



	/* dq */

	ret = hpre_crt_para_get(ctx->rsa.crt_prikey, rsa_key->dq,

				rsa_key->dq_sz, hlf_ksz);

	if (ret)

		goto free_key;



	/* dp */

	offset = hlf_ksz;

	ret = hpre_crt_para_get(ctx->rsa.crt_prikey + offset, rsa_key->dp,

				rsa_key->dp_sz, hlf_ksz);

	if (ret)

		goto free_key;



	/* q */

	offset = hlf_ksz * _CRT_Q;

	offset = hlf_ksz * HPRE_CRT_Q;

	ret = hpre_crt_para_get(ctx->rsa.crt_prikey + offset,

				rsa_key->q, rsa_key->q_sz, hlf_ksz);

	if (ret)

		goto free_key;



	/* p */

	offset = hlf_ksz * _CRT_P;

	offset = hlf_ksz * HPRE_CRT_P;

	ret = hpre_crt_para_get(ctx->rsa.crt_prikey + offset,

				rsa_key->p, rsa_key->p_sz, hlf_ksz);

	if (ret)

		goto free_key;



	/* qinv */

	offset = hlf_ksz * _CRT_INV;

	offset = hlf_ksz * HPRE_CRT_INV;

	ret = hpre_crt_para_get(ctx->rsa.crt_prikey + offset,

				rsa_key->qinv, rsa_key->qinv_sz, hlf_ksz);

	if (ret)

		goto free_key;



	ctx->crt_g2_mode = true;



	return 0;



free_key:

	memset(ctx->rsa.crt_prikey, '\0', hlf_ksz * _CRT_PRMS);

	dma_free_coherent(dev, hlf_ksz * _CRT_PRMS, ctx->rsa.crt_prikey,

	memset(ctx->rsa.crt_prikey, 0, hlf_ksz * HPRE_CRT_PRMS);

	dma_free_coherent(dev, hlf_ksz * HPRE_CRT_PRMS, ctx->rsa.crt_prikey,

			  ctx->rsa.dma_crt_prikey);

	ctx->rsa.crt_prikey = NULL;

	ctx->crt_g2_mode = false;
@@ -897,7 +900,7 @@ static int hpre_rsa_setkey_crt(struct hpre_ctx *ctx, struct rsa_key *rsa_key) 
static void hpre_rsa_clear_ctx(struct hpre_ctx *ctx, bool is_exit)

{

	unsigned int half_key_sz = ctx->key_sz >> 1;

	struct device *dev = &GET_DEV(ctx);

	struct device *dev = &HPRE_DEV(ctx);



	if (is_exit)

		hisi_qm_stop_qp(ctx->qp);
@@ -907,31 +910,31 @@ static void hpre_rsa_clear_ctx(struct hpre_ctx *ctx, bool is_exit) 
				  ctx->rsa.pubkey, ctx->rsa.dma_pubkey);

		ctx->rsa.pubkey = NULL;

	}



	if (ctx->rsa.crt_prikey) {

		memset(ctx->rsa.crt_prikey, '\0', half_key_sz * _CRT_PRMS);

		dma_free_coherent(dev, half_key_sz * _CRT_PRMS,

		memset(ctx->rsa.crt_prikey, 0, half_key_sz * HPRE_CRT_PRMS);

		dma_free_coherent(dev, half_key_sz * HPRE_CRT_PRMS,

				  ctx->rsa.crt_prikey, ctx->rsa.dma_crt_prikey);

		ctx->rsa.crt_prikey = NULL;

	}



	if (ctx->rsa.prikey) {

		memset(ctx->rsa.prikey, '\0', ctx->key_sz);

		memset(ctx->rsa.prikey, 0, ctx->key_sz);

		dma_free_coherent(dev, ctx->key_sz << 1, ctx->rsa.prikey,

				  ctx->rsa.dma_prikey);

		ctx->rsa.prikey = NULL;

	}



	_ctx_clear(ctx, is_exit);

	hpre_ctx_clear(ctx, is_exit);

}



static bool hpre_is_crt_key(struct rsa_key *key)

{

	u16 len = key->p_sz + key->q_sz + key->dp_sz + key->dq_sz +

		  key->qinv_sz;

#define LEN_OF_NCRT_PARA	5

	if (len <= LEN_OF_NCRT_PARA)

		return false;

	else

		return true;



#define LEN_OF_NCRT_PARA	5 //N-CRT less than 5 parameters

	return len > LEN_OF_NCRT_PARA;

}



static int hpre_rsa_setkey(struct hpre_ctx *ctx, const void *key,
@@ -957,25 +960,15 @@ static int hpre_rsa_setkey(struct hpre_ctx *ctx, const void *key, 
		ret = hpre_rsa_set_d(ctx, rsa_key.d, rsa_key.d_sz);

		if (ret < 0)

			goto free;

	       /**

		* The sample of pkcs1pad_rsa_tv_template is deferent,

		* between the kernel before and after 4.17,

		* we should judge it is CRT or not,

		* regardless of the kernel version,

		* CRT: return true,  N-CRT: return false .

		*/

		if (hpre_is_crt_key(&rsa_key))

			hpre_rsa_setkey_crt(ctx, &rsa_key);

	}



	ret = hpre_rsa_set_e(ctx, rsa_key.e, rsa_key.e_sz);

	if (ret < 0)

		goto free;



	if (!ctx->rsa.pubkey) {

		ret = -EINVAL;

		goto free;

	}

	if (private && !ctx->rsa.prikey) {

	if ((private && !ctx->rsa.prikey) || !ctx->rsa.pubkey) {

		ret = -EINVAL;

		goto free;

	}
@@ -995,6 +988,7 @@ static int hpre_rsa_setpubkey(struct crypto_akcipher *tfm, const void *key, 
	ret = crypto_akcipher_set_pub_key(ctx->rsa.soft_tfm, key, keylen);

	if (ret)

		return ret;



	return hpre_rsa_setkey(ctx, key, keylen, false);

}
@@ -1084,24 +1078,36 @@ static struct kpp_alg dh = { 


int hpre_algs_register(void)

{

	int ret;

	int ret = EINVAL;



	mutex_lock(&hpre_alg_lock);

	if (++hpre_active_devs == 1) {

		rsa.base.cra_flags = 0;

		ret = crypto_register_akcipher(&rsa);

		if (ret)

		return ret;



			goto unlock;

#ifdef CONFIG_CRYPTO_DH

	return crypto_register_kpp(&dh);

#else

	return ret;

		ret = crypto_register_kpp(&dh);

		if (ret) {

			crypto_unregister_akcipher(&rsa);

			goto unlock;

		}

#endif

	}



unlock:

	mutex_unlock(&hpre_alg_lock);

	return ret;

}



void hpre_algs_unregister(void)

{

	mutex_lock(&hpre_alg_lock);

	if (--hpre_active_devs == 0) {

		crypto_unregister_akcipher(&rsa);

#ifdef CONFIG_CRYPTO_DH

		crypto_unregister_kpp(&dh);

#endif

	}

	mutex_unlock(&hpre_alg_lock);

}

drivers/crypto/hisilicon/hpre/hpre_main.c

+133 −159

File changed.

Preview size limit exceeded, changes collapsed.