Commit 4e43cd63 authored by Peng Fan's avatar Peng Fan Committed by Shawn Guo
Browse files

arm64: dts: imx8qxp: correct usdhc clock-names sequence 



Per dt-bindings, the clock-names sequence should be ipg ahb per to pass
dtbs_check.

Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 40ba2eda

arch/arm64/boot/dts/freescale/imx8qxp.dtsi

+9 −9
Original line number Diff line number Diff line
@@ -366,9 +366,9 @@ 
			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;

			reg = <0x5b010000 0x10000>;

			clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC0_IPG_CLK>,

				 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>,

				 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>;

			clock-names = "ipg", "per", "ahb";

				 <&conn_lpcg IMX_CONN_LPCG_SDHC0_HCLK>,

				 <&conn_lpcg IMX_CONN_LPCG_SDHC0_PER_CLK>;

			clock-names = "ipg", "ahb", "per";

			power-domains = <&pd IMX_SC_R_SDHC_0>;

			status = "disabled";

		};
@@ -378,9 +378,9 @@ 
			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;

			reg = <0x5b020000 0x10000>;

			clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC1_IPG_CLK>,

				 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>,

				 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>;

			clock-names = "ipg", "per", "ahb";

				 <&conn_lpcg IMX_CONN_LPCG_SDHC1_HCLK>,

				 <&conn_lpcg IMX_CONN_LPCG_SDHC1_PER_CLK>;

			clock-names = "ipg", "ahb", "per";

			power-domains = <&pd IMX_SC_R_SDHC_1>;

			fsl,tuning-start-tap = <20>;

			fsl,tuning-step= <2>;
@@ -392,9 +392,9 @@ 
			interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;

			reg = <0x5b030000 0x10000>;

			clocks = <&conn_lpcg IMX_CONN_LPCG_SDHC2_IPG_CLK>,

				 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>,

				 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>;

			clock-names = "ipg", "per", "ahb";

				 <&conn_lpcg IMX_CONN_LPCG_SDHC2_HCLK>,

				 <&conn_lpcg IMX_CONN_LPCG_SDHC2_PER_CLK>;

			clock-names = "ipg", "ahb", "per";

			power-domains = <&pd IMX_SC_R_SDHC_2>;

			status = "disabled";

		};