Commit 4e42ccca authored by Jie Wang's avatar Jie Wang Committed by Jiantao Xiao
Browse files

net: hns3: add support PF provides customized interfaces to detect port faults. 

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I6YE0O


CVE: NA

----------------------------------------------------------------------

When the link status of the PF network port changes from up to down,
the IMP can quickly report the link down fault cause based on the
link status. If the hardware is faulty from the beginning and the
link is not up, the IMP does not report the link down event
because the status is not changed.

Therefore, an interface is provided to detect port faults.

Signed-off-by: default avatarJie Wang <wangjie125@huawei.com>
Signed-off-by: default avatarJiantao Xiao <xiaojiantao1@h-partners.com>
parent be633dee

drivers/net/ethernet/hisilicon/hns3/hnae3_ext.h

+15 −0
Original line number Diff line number Diff line
@@ -44,6 +44,8 @@ enum hnae3_ext_opcode { 
	HNAE3_EXT_OPC_GET_LANE_STATUS,

	HNAE3_EXT_OPC_DISABLE_CLOCK,

	HNAE3_EXT_OPC_SET_PFC_TIME,

	HNAE3_EXT_OPC_GET_HILINK_REF_LOS,

	HNAE3_EXT_OPC_GET_PORT_FAULT_STATUS,

};



struct hnae3_pfc_storm_para {
@@ -54,6 +56,19 @@ struct hnae3_pfc_storm_para { 
	u32 recovery_period_ms;

};



enum hnae3_port_fault_type {

	HNAE3_FAULT_TYPE_CDR_FLASH,

	HNAE3_FAULT_TYPE_9545_ERR,

	HNAE3_FAULT_TYPE_CDR_CORE,

	HNAE3_FAULT_TYPE_HILINK_REF_LOS,

	HNAE3_FAULT_TYPE_INVALID

};



struct hnae3_port_fault {

	u32 fault_type;

	u32 fault_status;

};



struct hnae3_notify_pkt_param {

	u32 ipg;     /* inter-packet gap of sending, the unit is one cycle of clock */

	u16 num;     /* packet number of sending */

drivers/net/ethernet/hisilicon/hns3/hns3_ext.c

+22 −0
Original line number Diff line number Diff line
@@ -439,3 +439,25 @@ int nic_set_pfc_time_cfg(struct net_device *ndev, u16 time) 
				  &time, sizeof(time));

}

EXPORT_SYMBOL(nic_set_pfc_time_cfg);



int nic_get_port_fault_status(struct net_device *ndev, u32 fault_type, u32 *status)

{

	int opcode = HNAE3_EXT_OPC_GET_PORT_FAULT_STATUS;

	struct hnae3_port_fault fault_para;

	int ret;



	if (!status)

		return -EINVAL;



	if (fault_type == HNAE3_FAULT_TYPE_HILINK_REF_LOS)

		opcode = HNAE3_EXT_OPC_GET_HILINK_REF_LOS;



	fault_para.fault_type = fault_type;

	ret = nic_invoke_pri_ops(ndev, opcode, &fault_para, sizeof(fault_para));

	if (ret)

		return ret;



	*status = fault_para.fault_status;

	return 0;

}

EXPORT_SYMBOL(nic_get_port_fault_status);

drivers/net/ethernet/hisilicon/hns3/hns3_ext.h

+6 −0
Original line number Diff line number Diff line
@@ -14,6 +14,11 @@ 
#define HNS3_PFC_STORM_PARA_PERIOD_MIN 5

#define HNS3_PFC_STORM_PARA_PERIOD_MAX 2000



#define nic_get_cdr_flash_status(ndev, status)	\

	nic_get_port_fault_status(ndev, HNAE3_FAULT_TYPE_CDR_FLASH, status)

#define nic_get_hilink_ref_los(ndev, status)	\

	nic_get_port_fault_status(ndev, HNAE3_FAULT_TYPE_HILINK_REF_LOS, status)



int nic_netdev_match_check(struct net_device *netdev);

void nic_chip_recover_handler(struct net_device *ndev,

			      enum hnae3_event_type_custom event_t);
@@ -42,4 +47,5 @@ int nic_disable_net_lane(struct net_device *ndev); 
int nic_get_net_lane_status(struct net_device *ndev, u32 *status);

int nic_disable_clock(struct net_device *ndev);

int nic_set_pfc_time_cfg(struct net_device *ndev, u16 time);

int nic_get_port_fault_status(struct net_device *ndev, u32 fault_type, u32 *status);

#endif

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

+6 −0
Original line number Diff line number Diff line
@@ -355,6 +355,12 @@ struct hclge_sfp_info_cmd { 
	u8 rsv[6];

};



struct hclge_port_fault_cmd {

	__le32 fault_status;

	__le32 port_type;

	u8 rsv[16];

};



#define HCLGE_MAC_CFG_FEC_AUTO_EN_B	0

#define HCLGE_MAC_CFG_FEC_MODE_S	1

#define HCLGE_MAC_CFG_FEC_MODE_M	GENMASK(3, 1)

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ext.c

+52 −0
Original line number Diff line number Diff line
@@ -582,6 +582,56 @@ static int hclge_set_pause_trans_time(struct hclge_dev *hdev, void *data, 
	return 0;

}



static int hclge_get_hilink_ref_los(struct hclge_dev *hdev, void *data,

				    size_t length)

{

	struct hclge_port_fault_cmd *fault_cmd;

	struct hclge_desc desc;

	int ret;



	if (length != sizeof(struct hnae3_port_fault))

		return -EINVAL;



	fault_cmd = (struct hclge_port_fault_cmd *)desc.data;

	ret = hclge_get_info_from_cmd(hdev, &desc, 1, HCLGE_OPC_CFG_GET_HILINK_REF_LOS);

	if (ret) {

		dev_err(&hdev->pdev->dev,

			"failed to get hilink ref los, ret = %d\n", ret);

		return ret;

	}



	*(u32 *)data = le32_to_cpu(fault_cmd->fault_status);

	return 0;

}



static int hclge_get_port_fault_status(struct hclge_dev *hdev, void *data,

				       size_t length)

{

	struct hclge_port_fault_cmd *fault_cmd;

	struct hnae3_port_fault *para;

	struct hclge_desc desc;

	int ret;



	if (length != sizeof(struct hnae3_port_fault))

		return -EINVAL;



	para = (struct hnae3_port_fault *)data;

	fault_cmd = (struct hclge_port_fault_cmd *)desc.data;

	hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_GET_PORT_FAULT_STATUS, true);

	fault_cmd->port_type = cpu_to_le32(para->fault_type);

	ret = hclge_cmd_send(&hdev->hw, &desc, 1);

	if (ret) {

		dev_err(&hdev->pdev->dev,

			"failed to get port fault status, type = %u, ret = %d\n",

			para->fault_type, ret);

		return ret;

	}



	para->fault_status = le32_to_cpu(fault_cmd->fault_status);



	return 0;

}



static void hclge_ext_resotre_config(struct hclge_dev *hdev)

{

	if (hdev->reset_type != HNAE3_IMP_RESET &&
@@ -749,6 +799,8 @@ static const hclge_priv_ops_fn hclge_ext_func_arr[] = { 
	[HNAE3_EXT_OPC_GET_LANE_STATUS] = hclge_get_net_lane_status,

	[HNAE3_EXT_OPC_DISABLE_CLOCK] = hclge_disable_nic_clock,

	[HNAE3_EXT_OPC_SET_PFC_TIME] = hclge_set_pause_trans_time,

	[HNAE3_EXT_OPC_GET_HILINK_REF_LOS] = hclge_get_hilink_ref_los,

	[HNAE3_EXT_OPC_GET_PORT_FAULT_STATUS] = hclge_get_port_fault_status,

};



int hclge_ext_ops_handle(struct hnae3_handle *handle, int opcode,