Commit 4e181ded authored by Daniel Vetter's avatar Daniel Vetter
Browse files

Merge tag 'drm-intel-fixes-2021-01-07' of... 

Merge tag 'drm-intel-fixes-2021-01-07' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

drm/i915 fixes for v5.11-rc3:
- Use per-connector PM QoS tracking for DP aux communication
- GuC firmware fix for older Cometlakes
- Clear the gpu reloc and shadow batches

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/877dop18zf.fsf@intel.com
parents 57cda5e9 9397d662

drivers/gpu/drm/i915/display/intel_display_types.h

+3 −0
Original line number Diff line number Diff line
@@ -1436,6 +1436,9 @@ struct intel_dp { 
		bool ycbcr_444_to_420;

	} dfp;



	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */

	struct pm_qos_request pm_qos;



	/* Display stream compression testing */

	bool force_dsc_en;

drivers/gpu/drm/i915/display/intel_dp.c

+6 −2
Original line number Diff line number Diff line
@@ -1489,7 +1489,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, 
	 * lowest possible wakeup latency and so prevent the cpu from going into

	 * deep sleep states.

	 */

	cpu_latency_qos_update_request(&i915->pm_qos, 0);

	cpu_latency_qos_update_request(&intel_dp->pm_qos, 0);



	intel_dp_check_edp(intel_dp);
@@ -1622,7 +1622,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, 


	ret = recv_bytes;

out:

	cpu_latency_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE);

	cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);



	if (vdd)

		edp_panel_vdd_off(intel_dp, false);
@@ -1898,6 +1898,9 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) 
static void

intel_dp_aux_fini(struct intel_dp *intel_dp)

{

	if (cpu_latency_qos_request_active(&intel_dp->pm_qos))

		cpu_latency_qos_remove_request(&intel_dp->pm_qos);



	kfree(intel_dp->aux.name);

}
@@ -1950,6 +1953,7 @@ intel_dp_aux_init(struct intel_dp *intel_dp) 
					       encoder->base.name);



	intel_dp->aux.transfer = intel_dp_aux_transfer;

	cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE);

}



bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

+3 −1
Original line number Diff line number Diff line
@@ -1046,7 +1046,7 @@ static void reloc_gpu_flush(struct i915_execbuffer *eb, struct reloc_cache *cach 
	GEM_BUG_ON(cache->rq_size >= obj->base.size / sizeof(u32));

	cache->rq_cmd[cache->rq_size] = MI_BATCH_BUFFER_END;



	__i915_gem_object_flush_map(obj, 0, sizeof(u32) * (cache->rq_size + 1));

	i915_gem_object_flush_map(obj);

	i915_gem_object_unpin_map(obj);



	intel_gt_chipset_flush(cache->rq->engine->gt);
@@ -1296,6 +1296,8 @@ static int __reloc_gpu_alloc(struct i915_execbuffer *eb, 
		goto err_pool;

	}



	memset32(cmd, 0, pool->obj->base.size / sizeof(u32));



	batch = i915_vma_instance(pool->obj, vma->vm, NULL);

	if (IS_ERR(batch)) {

		err = PTR_ERR(batch);

drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c

+1 −0
Original line number Diff line number Diff line
@@ -53,6 +53,7 @@ void intel_uc_fw_change_status(struct intel_uc_fw *uc_fw, 
	fw_def(ELKHARTLAKE, 0, guc_def(ehl, 49, 0, 1), huc_def(ehl,  9, 0, 0)) \

	fw_def(ICELAKE,     0, guc_def(icl, 49, 0, 1), huc_def(icl,  9, 0, 0)) \

	fw_def(COMETLAKE,   5, guc_def(cml, 49, 0, 1), huc_def(cml,  4, 0, 0)) \

	fw_def(COMETLAKE,   0, guc_def(kbl, 49, 0, 1), huc_def(kbl,  4, 0, 0)) \

	fw_def(COFFEELAKE,  0, guc_def(kbl, 49, 0, 1), huc_def(kbl,  4, 0, 0)) \

	fw_def(GEMINILAKE,  0, guc_def(glk, 49, 0, 1), huc_def(glk,  4, 0, 0)) \

	fw_def(KABYLAKE,    0, guc_def(kbl, 49, 0, 1), huc_def(kbl,  4, 0, 0)) \

drivers/gpu/drm/i915/i915_cmd_parser.c

+9 −18
Original line number Diff line number Diff line
@@ -1166,7 +1166,7 @@ static u32 *copy_batch(struct drm_i915_gem_object *dst_obj, 
		}

	}

	if (IS_ERR(src)) {

		unsigned long x, n;

		unsigned long x, n, remain;

		void *ptr;



		/*
@@ -1177,14 +1177,15 @@ static u32 *copy_batch(struct drm_i915_gem_object *dst_obj, 
		 * We don't care about copying too much here as we only

		 * validate up to the end of the batch.

		 */

		remain = length;

		if (!(dst_obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ))

			length = round_up(length,

			remain = round_up(remain,

					  boot_cpu_data.x86_clflush_size);



		ptr = dst;

		x = offset_in_page(offset);

		for (n = offset >> PAGE_SHIFT; length; n++) {

			int len = min(length, PAGE_SIZE - x);

		for (n = offset >> PAGE_SHIFT; remain; n++) {

			int len = min(remain, PAGE_SIZE - x);



			src = kmap_atomic(i915_gem_object_get_page(src_obj, n));

			if (needs_clflush)
@@ -1193,13 +1194,15 @@ static u32 *copy_batch(struct drm_i915_gem_object *dst_obj, 
			kunmap_atomic(src);



			ptr += len;

			length -= len;

			remain -= len;

			x = 0;

		}

	}



	i915_gem_object_unpin_pages(src_obj);



	memset32(dst + length, 0, (dst_obj->base.size - length) / sizeof(u32));



	/* dst_obj is returned with vmap pinned */

	return dst;

}
@@ -1392,11 +1395,6 @@ static unsigned long *alloc_whitelist(u32 batch_length) 


#define LENGTH_BIAS 2



static bool shadow_needs_clflush(struct drm_i915_gem_object *obj)

{

	return !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE);

}



/**

 * intel_engine_cmd_parser() - parse a batch buffer for privilege violations

 * @engine: the engine on which the batch is to execute
@@ -1538,16 +1536,9 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine, 
				ret = 0; /* allow execution */

			}

		}



		if (shadow_needs_clflush(shadow->obj))

			drm_clflush_virt_range(batch_end, 8);

	}



	if (shadow_needs_clflush(shadow->obj)) {

		void *ptr = page_mask_bits(shadow->obj->mm.mapping);



		drm_clflush_virt_range(ptr, (void *)(cmd + 1) - ptr);

	}

	i915_gem_object_flush_map(shadow->obj);



	if (!IS_ERR_OR_NULL(jump_whitelist))

		kfree(jump_whitelist);