Commit 4df7e2c8 authored by Nicholas Kazlauskas's avatar Nicholas Kazlauskas Committed by Alex Deucher
Browse files

drm/amd/display: Update SR watermarks for DCN314 



[Why & How]
New values requested by hardware after fine-tuning.
Update for all memory types.

Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarAlan Liu <HaoPing.Liu@amd.com>
Signed-off-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 1a2b886b

drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c

+16 −16
Original line number Original line Diff line number Diff line
@@ -363,32 +363,32 @@ static struct wm_table ddr5_wm_table = { 
			.wm_inst = WM_A,

			.wm_inst = WM_A,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.72,

			.pstate_latency_us = 11.72,

			.sr_exit_time_us = 9,

			.sr_exit_time_us = 12.5,

			.sr_enter_plus_exit_time_us = 11,

			.sr_enter_plus_exit_time_us = 14.5,

			.valid = true,

			.valid = true,

		},

		},

		{

		{

			.wm_inst = WM_B,

			.wm_inst = WM_B,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.72,

			.pstate_latency_us = 11.72,

			.sr_exit_time_us = 9,

			.sr_exit_time_us = 12.5,

			.sr_enter_plus_exit_time_us = 11,

			.sr_enter_plus_exit_time_us = 14.5,

			.valid = true,

			.valid = true,

		},

		},

		{

		{

			.wm_inst = WM_C,

			.wm_inst = WM_C,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.72,

			.pstate_latency_us = 11.72,

			.sr_exit_time_us = 9,

			.sr_exit_time_us = 12.5,

			.sr_enter_plus_exit_time_us = 11,

			.sr_enter_plus_exit_time_us = 14.5,

			.valid = true,

			.valid = true,

		},

		},

		{

		{

			.wm_inst = WM_D,

			.wm_inst = WM_D,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.72,

			.pstate_latency_us = 11.72,

			.sr_exit_time_us = 9,

			.sr_exit_time_us = 12.5,

			.sr_enter_plus_exit_time_us = 11,

			.sr_enter_plus_exit_time_us = 14.5,

			.valid = true,

			.valid = true,

		},

		},

	}

	}
@@ -400,32 +400,32 @@ static struct wm_table lpddr5_wm_table = { 
			.wm_inst = WM_A,

			.wm_inst = WM_A,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 11.5,

			.sr_exit_time_us = 16.5,

			.sr_enter_plus_exit_time_us = 14.5,

			.sr_enter_plus_exit_time_us = 18.5,

			.valid = true,

			.valid = true,

		},

		},

		{

		{

			.wm_inst = WM_B,

			.wm_inst = WM_B,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 11.5,

			.sr_exit_time_us = 16.5,

			.sr_enter_plus_exit_time_us = 14.5,

			.sr_enter_plus_exit_time_us = 18.5,

			.valid = true,

			.valid = true,

		},

		},

		{

		{

			.wm_inst = WM_C,

			.wm_inst = WM_C,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 11.5,

			.sr_exit_time_us = 16.5,

			.sr_enter_plus_exit_time_us = 14.5,

			.sr_enter_plus_exit_time_us = 18.5,

			.valid = true,

			.valid = true,

		},

		},

		{

		{

			.wm_inst = WM_D,

			.wm_inst = WM_D,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.wm_type = WM_TYPE_PSTATE_CHG,

			.pstate_latency_us = 11.65333,

			.pstate_latency_us = 11.65333,

			.sr_exit_time_us = 11.5,

			.sr_exit_time_us = 16.5,

			.sr_enter_plus_exit_time_us = 14.5,

			.sr_enter_plus_exit_time_us = 18.5,

			.valid = true,

			.valid = true,

		},

		},

	}

	}

drivers/gpu/drm/amd/display/dc/dml/dcn314/dcn314_fpu.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -146,8 +146,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_14_soc = { 
		},

		},

	},

	},

	.num_states = 5,

	.num_states = 5,

	.sr_exit_time_us = 9.0,

	.sr_exit_time_us = 16.5,

	.sr_enter_plus_exit_time_us = 11.0,

	.sr_enter_plus_exit_time_us = 18.5,

	.sr_exit_z8_time_us = 442.0,

	.sr_exit_z8_time_us = 442.0,

	.sr_enter_plus_exit_z8_time_us = 560.0,

	.sr_enter_plus_exit_z8_time_us = 560.0,

	.writeback_latency_us = 12.0,

	.writeback_latency_us = 12.0,