Commit 4de23dca authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915/pvc: Read correct RP_STATE_CAP register 



The SoC registers, including RP_STATE_CAP, have moved to a new location
in GTTMMADR on Ponte Vecchio.  We need to update the register offset
accordingly.

Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505213812.3979301-5-matthew.d.roper@intel.com
parent 9d67edba

drivers/gpu/drm/i915/gt/intel_rps.c

+3 −1
Original line number Diff line number Diff line
@@ -1075,7 +1075,9 @@ static u32 intel_rps_read_state_cap(struct intel_rps *rps) 
	struct drm_i915_private *i915 = rps_to_i915(rps);

	struct intel_uncore *uncore = rps_to_uncore(rps);



	if (IS_XEHPSDV(i915))

	if (IS_PONTEVECCHIO(i915))

		return intel_uncore_read(uncore, PVC_RP_STATE_CAP);

	else if (IS_XEHPSDV(i915))

		return intel_uncore_read(uncore, XEHPSDV_RP_STATE_CAP);

	else if (IS_GEN9_LP(i915))

		return intel_uncore_read(uncore, BXT_RP_STATE_CAP);

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -1845,6 +1845,7 @@ 
#define BXT_RP_STATE_CAP        _MMIO(0x138170)

#define GEN9_RP_STATE_LIMITS	_MMIO(0x138148)

#define XEHPSDV_RP_STATE_CAP	_MMIO(0x250014)

#define PVC_RP_STATE_CAP	_MMIO(0x281014)



#define GT0_PERF_LIMIT_REASONS		_MMIO(0x1381a8)

#define   GT0_PERF_LIMIT_REASONS_MASK	0xde3