Commit 4dd52392 authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'coresight-fixes-v6.3' of... 

Merge tag 'coresight-fixes-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux

 into char-misc-linus

Suzuki writes:

coresight: Fixes for v6.3

Fixes for coresight subsystem includes:
 - Fix etm4_enable_hw to program all the address comparator pairs (instead of
   half of them)
 - Do not access TRCIDR1 register without OSLK cleared in etm4_probe for mmio
   access.

Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>

* tag 'coresight-fixes-v6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux:
  coresight: etm4x: Do not access TRCIDR1 for identification
  coresight-etm4: Fix for() loop drvdata->nr_addr_cmp range bug
parents 84052541 735e7b30

drivers/hwtracing/coresight/coresight-etm4x-core.c

+10 −14
Original line number Diff line number Diff line
@@ -472,7 +472,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) 
		if (etm4x_sspcicrn_present(drvdata, i))

			etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i));

	}

	for (i = 0; i < drvdata->nr_addr_cmp; i++) {

	for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {

		etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));

		etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));

	}
@@ -1070,25 +1070,21 @@ static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata, 
				   struct csdev_access *csa)

{

	u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH);

	u32 idr1 = readl_relaxed(drvdata->base + TRCIDR1);



	/*

	 * All ETMs must implement TRCDEVARCH to indicate that

	 * the component is an ETMv4. To support any broken

	 * implementations we fall back to TRCIDR1 check, which

	 * is not really reliable.

	 * the component is an ETMv4. Even though TRCIDR1 also

	 * contains the information, it is part of the "Trace"

	 * register and must be accessed with the OSLK cleared,

	 * with MMIO. But we cannot touch the OSLK until we are

	 * sure this is an ETM. So rely only on the TRCDEVARCH.

	 */

	if ((devarch & ETM_DEVARCH_ID_MASK) == ETM_DEVARCH_ETMv4x_ARCH) {

		drvdata->arch = etm_devarch_to_arch(devarch);

	} else {

		pr_warn("CPU%d: ETM4x incompatible TRCDEVARCH: %x, falling back to TRCIDR1\n",

			smp_processor_id(), devarch);



		if (ETM_TRCIDR1_ARCH_MAJOR(idr1) != ETM_TRCIDR1_ARCH_ETMv4)

	if ((devarch & ETM_DEVARCH_ID_MASK) != ETM_DEVARCH_ETMv4x_ARCH) {

		pr_warn_once("TRCDEVARCH doesn't match ETMv4 architecture\n");

		return false;

		drvdata->arch = etm_trcidr_to_arch(idr1);

	}



	drvdata->arch = etm_devarch_to_arch(devarch);

	*csa = CSDEV_ACCESS_IOMEM(drvdata->base);

	return true;

}

drivers/hwtracing/coresight/coresight-etm4x.h

+6 −14
Original line number Diff line number Diff line
@@ -753,14 +753,12 @@ 
 * TRCDEVARCH	- CoreSight architected register

 *                - Bits[15:12] - Major version

 *                - Bits[19:16] - Minor version

 * TRCIDR1	- ETM architected register

 *                - Bits[11:8] - Major version

 *                - Bits[7:4]  - Minor version

 * We must rely on TRCDEVARCH for the version information,

 * however we don't want to break the support for potential

 * old implementations which might not implement it. Thus

 * we fall back to TRCIDR1 if TRCDEVARCH is not implemented

 * for memory mapped components.

 *

 * We must rely only on TRCDEVARCH for the version information. Even though,

 * TRCIDR1 also provides the architecture version, it is a "Trace" register

 * and as such must be accessed only with Trace power domain ON. This may

 * not be available at probe time.

 *

 * Now to make certain decisions easier based on the version

 * we use an internal representation of the version in the

 * driver, as follows :
@@ -786,12 +784,6 @@ static inline u8 etm_devarch_to_arch(u32 devarch) 
				ETM_DEVARCH_REVISION(devarch));

}



static inline u8 etm_trcidr_to_arch(u32 trcidr1)

{

	return ETM_ARCH_VERSION(ETM_TRCIDR1_ARCH_MAJOR(trcidr1),

				ETM_TRCIDR1_ARCH_MINOR(trcidr1));

}



enum etm_impdef_type {

	ETM4_IMPDEF_HISI_CORE_COMMIT,

	ETM4_IMPDEF_FEATURE_MAX,