Unverified Commit 4d9596d4 authored by Judy Hsiao's avatar Judy Hsiao Committed by Mark Brown
Browse files

ASoC: qcom: Use MCLK as RT5682I-VS sysclk source 



Both MCLK and BCLK can be the clock source of sysclk via PLL
according to its datasheet.
This patch sets MCLK as the clock source as we use MCLK in the
previous projects.

Fixes: c5198db8 ("ASoC: qcom: Add driver support for ALC5682I-VS")
Signed-off-by: default avatarJudy Hsiao <judyhsiao@chromium.org>
Link: https://lore.kernel.org/r/20220419062952.356017-1-judyhsiao@chromium.org


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 666b0cad

sound/soc/qcom/sc7280.c

+5 −5
Original line number Original line Diff line number Diff line
@@ -21,7 +21,7 @@ 
#include "lpass.h"

#include "lpass.h"





#define DEFAULT_MCLK_RATE              19200000

#define DEFAULT_MCLK_RATE              19200000

#define RT5682_PLL1_FREQ (48000 * 512)

#define RT5682_PLL_FREQ (48000 * 512)





struct sc7280_snd_data {

struct sc7280_snd_data {

	struct snd_soc_card card;

	struct snd_soc_card card;
@@ -137,15 +137,15 @@ static int sc7280_rt5682_init(struct snd_soc_pcm_runtime *rtd) 
				SND_SOC_DAIFMT_NB_NF |

				SND_SOC_DAIFMT_NB_NF |

				SND_SOC_DAIFMT_I2S);

				SND_SOC_DAIFMT_I2S);





	ret = snd_soc_dai_set_pll(codec_dai, RT5682S_PLL1, RT5682S_PLL_S_BCLK1,

	ret = snd_soc_dai_set_pll(codec_dai, RT5682S_PLL2, RT5682S_PLL_S_MCLK,

					1536000, RT5682_PLL1_FREQ);

					DEFAULT_MCLK_RATE, RT5682_PLL_FREQ);

	if (ret) {

	if (ret) {

		dev_err(rtd->dev, "can't set codec pll: %d\n", ret);

		dev_err(rtd->dev, "can't set codec pll: %d\n", ret);

		return ret;

		return ret;

	}

	}





	ret = snd_soc_dai_set_sysclk(codec_dai, RT5682S_SCLK_S_PLL1,

	ret = snd_soc_dai_set_sysclk(codec_dai, RT5682S_SCLK_S_PLL2,

					RT5682_PLL1_FREQ,

					RT5682_PLL_FREQ,

					SND_SOC_CLOCK_IN);

					SND_SOC_CLOCK_IN);





	if (ret) {

	if (ret) {