Commit 4d877b1a authored by Daniel Vetter's avatar Daniel Vetter
Browse files

Merge tag 'drm-intel-next-2023-04-06' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



- Fix DPT+shmem combo and add i915.enable_dpt modparam (Ville)
- i915.enable_sagv module parameter (Ville)
- Correction to QGV related register addresses (Vinod)
- IPS debugfs per-crtc and new file for false_color (Ville)
- More clean-up and reorganization of Display code (Jani)
- DP DSC related fixes and improvements (Stanislav, Ankit, Suraj, Swati)
- Make utility pin asserts more accurate (Ville)
- Meteor Lake enabling (Daniele)
- High refresh rate PSR fixes (Jouni)
- Cursor and Plane chicken register fixes (Ville)
- Align the ADL-P TypeC sequences with hardware specification (Imre)
- Documentation build fixes and improvements to catch bugs earlier (Lee, Jani)
- PL1 power limit hwmon entry changed to use 0 as disabled state (Ashutosh)
- DP aux sync fix and improvements (Ville)
- DP MST fixes and w/a (Stanislav)
- Limit PXP drm-errors or warning on firmware API failures (Alan)

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZC7RR3Laet8ywHRo@intel.com
parents 8904a1e2 b358793c

Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon

+3 −1
Original line number Diff line number Diff line
@@ -14,7 +14,9 @@ Description: RW. Card reactive sustained (PL1/Tau) power limit in microwatts. 


		The power controller will throttle the operating frequency

		if the power averaged over a window (typically seconds)

		exceeds this limit.

		exceeds this limit. A read value of 0 means that the PL1

		power limit is disabled, writing 0 disables the

		limit. Writing values > 0 will enable the power limit.



		Only supported for particular Intel i915 graphics platforms.

drivers/gpu/drm/i915/Kconfig

+0 −6
Original line number Diff line number Diff line
@@ -164,11 +164,5 @@ menu "drm/i915 Profile Guided Optimisation" 
	source "drivers/gpu/drm/i915/Kconfig.profile"

endmenu



menu "drm/i915 Unstable Evolution"

	visible if EXPERT && STAGING && BROKEN

	depends on DRM_I915

	source "drivers/gpu/drm/i915/Kconfig.unstable"

endmenu



config DRM_I915_GVT

	bool

drivers/gpu/drm/i915/Kconfig.unstable

deleted100644 → 0
+0 −21
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only

config DRM_I915_UNSTABLE

	bool "Enable unstable API for early prototype development"

	depends on EXPERT

	depends on STAGING

	depends on BROKEN # should never be enabled by distros!

	# We use the dependency on !COMPILE_TEST to not be enabled in

	# allmodconfig or allyesconfig configurations

	depends on !COMPILE_TEST

	default n

	help

	  Enable prototype uAPI under general discussion before they are

	  finalized. Such prototypes may be withdrawn or substantially

	  changed before release. They are only enabled here so that a wide

	  number of interested parties (userspace driver developers) can

	  verify that the uAPI meet their expectations. These uAPI should

	  never be used in production.



	  Recommended for driver developers _only_.



	  If in the slightest bit of doubt, say "N".

drivers/gpu/drm/i915/Makefile

+10 −2
Original line number Diff line number Diff line
@@ -47,10 +47,10 @@ i915-y += i915_driver.o \ 
	  i915_switcheroo.o \

	  i915_sysfs.o \

	  i915_utils.o \

	  intel_clock_gating.o \

	  intel_device_info.o \

	  intel_memory_region.o \

	  intel_pcode.o \

	  intel_pm.o \

	  intel_region_ttm.o \

	  intel_runtime_pm.o \

	  intel_sbi.o \
@@ -369,6 +369,13 @@ include $(src)/gvt/Makefile 
obj-$(CONFIG_DRM_I915) += i915.o

obj-$(CONFIG_DRM_I915_GVT_KVMGT) += kvmgt.o



# kernel-doc test

#

# Enable locally for CONFIG_DRM_I915_WERROR=y. See also scripts/Makefile.build

ifdef CONFIG_DRM_I915_WERROR

    cmd_checkdoc = $(srctree)/scripts/kernel-doc -none $<

endif



# header test



# exclude some broken headers from the test coverage
@@ -380,7 +387,8 @@ always-$(CONFIG_DRM_I915_WERROR) += \ 
		$(shell cd $(srctree)/$(src) && find * -name '*.h')))



quiet_cmd_hdrtest = HDRTEST $(patsubst %.hdrtest,%.h,$@)

      cmd_hdrtest = $(CC) $(filter-out $(CFLAGS_GCOV), $(c_flags)) -S -o /dev/null -x c /dev/null -include $<; touch $@

      cmd_hdrtest = $(CC) $(filter-out $(CFLAGS_GCOV), $(c_flags)) -S -o /dev/null -x c /dev/null -include $<; \

		$(srctree)/scripts/kernel-doc -none $<; touch $@



$(obj)/%.hdrtest: $(src)/%.h FORCE

	$(call if_changed_dep,hdrtest)

drivers/gpu/drm/i915/display/hsw_ips.c

+63 −10
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state) 
{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

	struct drm_i915_private *i915 = to_i915(crtc->base.dev);

	u32 val;



	if (!crtc_state->ips_enabled)

		return;
@@ -26,10 +27,15 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state) 
	drm_WARN_ON(&i915->drm,

		    !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));



	val = IPS_ENABLE;



	if (i915->display.ips.false_color)

		val |= IPS_FALSE_COLOR;



	if (IS_BROADWELL(i915)) {

		drm_WARN_ON(&i915->drm,

			    snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,

					    IPS_ENABLE | IPS_PCODE_CONTROL));

					    val | IPS_PCODE_CONTROL));

		/*

		 * Quoting Art Runyan: "its not safe to expect any particular

		 * value in IPS_CTL bit 31 after enabling IPS through the
@@ -37,7 +43,7 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state) 
		 * so we need to just enable it and continue on.

		 */

	} else {

		intel_de_write(i915, IPS_CTL, IPS_ENABLE);

		intel_de_write(i915, IPS_CTL, val);

		/*

		 * The bit only becomes 1 in the next vblank, so this wait here

		 * is essentially intel_wait_for_vblank. If we don't have this
@@ -268,14 +274,57 @@ void hsw_ips_get_config(struct intel_crtc_state *crtc_state) 
	}

}



static int hsw_ips_debugfs_false_color_get(void *data, u64 *val)

{

	struct intel_crtc *crtc = data;

	struct drm_i915_private *i915 = to_i915(crtc->base.dev);



	*val = i915->display.ips.false_color;



	return 0;

}



static int hsw_ips_debugfs_false_color_set(void *data, u64 val)

{

	struct intel_crtc *crtc = data;

	struct drm_i915_private *i915 = to_i915(crtc->base.dev);

	struct intel_crtc_state *crtc_state;

	int ret;



	ret = drm_modeset_lock(&crtc->base.mutex, NULL);

	if (ret)

		return ret;



	i915->display.ips.false_color = val;



	crtc_state = to_intel_crtc_state(crtc->base.state);



	if (!crtc_state->hw.active)

		goto unlock;



	if (crtc_state->uapi.commit &&

	    !try_wait_for_completion(&crtc_state->uapi.commit->hw_done))

		goto unlock;



	hsw_ips_enable(crtc_state);



 unlock:

	drm_modeset_unlock(&crtc->base.mutex);



	return ret;

}



DEFINE_DEBUGFS_ATTRIBUTE(hsw_ips_debugfs_false_color_fops,

			 hsw_ips_debugfs_false_color_get,

			 hsw_ips_debugfs_false_color_set,

			 "%llu\n");



static int hsw_ips_debugfs_status_show(struct seq_file *m, void *unused)

{

	struct drm_i915_private *i915 = m->private;

	struct intel_crtc *crtc = m->private;

	struct drm_i915_private *i915 = to_i915(crtc->base.dev);

	intel_wakeref_t wakeref;



	if (!HAS_IPS(i915))

		return -ENODEV;



	wakeref = intel_runtime_pm_get(&i915->runtime_pm);



	seq_printf(m, "Enabled by kernel parameter: %s\n",
@@ -297,10 +346,14 @@ static int hsw_ips_debugfs_status_show(struct seq_file *m, void *unused) 


DEFINE_SHOW_ATTRIBUTE(hsw_ips_debugfs_status);



void hsw_ips_debugfs_register(struct drm_i915_private *i915)

void hsw_ips_crtc_debugfs_add(struct intel_crtc *crtc)

{

	struct drm_minor *minor = i915->drm.primary;

	if (!hsw_crtc_supports_ips(crtc))

		return;



	debugfs_create_file("i915_ips_false_color", 0644, crtc->base.debugfs_entry,

			    crtc, &hsw_ips_debugfs_false_color_fops);



	debugfs_create_file("i915_ips_status", 0444, minor->debugfs_root,

			    i915, &hsw_ips_debugfs_status_fops);

	debugfs_create_file("i915_ips_status", 0444, crtc->base.debugfs_entry,

			    crtc, &hsw_ips_debugfs_status_fops);

}