Loading arch/arm/kvm/coproc.c +4 −4 Original line number Diff line number Diff line Loading @@ -478,15 +478,15 @@ static const struct coproc_reg cp15_regs[] = { /* ICC_SGI1R */ { CRm64(12), Op1( 0), is64, access_gic_sgi}, /* ICC_ASGI1R */ { CRm64(12), Op1( 1), is64, access_gic_sgi}, /* ICC_SGI0R */ { CRm64(12), Op1( 2), is64, access_gic_sgi}, /* VBAR: swapped by interrupt.S. */ { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32, NULL, reset_val, c12_VBAR, 0x00000000 }, /* ICC_ASGI1R */ { CRm64(12), Op1( 1), is64, access_gic_sgi}, /* ICC_SGI0R */ { CRm64(12), Op1( 2), is64, access_gic_sgi}, /* ICC_SRE */ { CRn(12), CRm(12), Op1( 0), Op2(5), is32, access_gic_sre }, Loading Loading
arch/arm/kvm/coproc.c +4 −4 Original line number Diff line number Diff line Loading @@ -478,15 +478,15 @@ static const struct coproc_reg cp15_regs[] = { /* ICC_SGI1R */ { CRm64(12), Op1( 0), is64, access_gic_sgi}, /* ICC_ASGI1R */ { CRm64(12), Op1( 1), is64, access_gic_sgi}, /* ICC_SGI0R */ { CRm64(12), Op1( 2), is64, access_gic_sgi}, /* VBAR: swapped by interrupt.S. */ { CRn(12), CRm( 0), Op1( 0), Op2( 0), is32, NULL, reset_val, c12_VBAR, 0x00000000 }, /* ICC_ASGI1R */ { CRm64(12), Op1( 1), is64, access_gic_sgi}, /* ICC_SGI0R */ { CRm64(12), Op1( 2), is64, access_gic_sgi}, /* ICC_SRE */ { CRn(12), CRm(12), Op1( 0), Op2(5), is32, access_gic_sre }, Loading