Commit 4cd8c315 authored by Srujana Challa's avatar Srujana Challa Committed by Herbert Xu
Browse files

crypto: octeontx2 - Add mailbox support for CN10K 



Mailbox region configuration has some changes on CN10K platform
from OcteonTX2(CN9XX) platform.

On CN10K platform:
The DRAM region allocated to PF is enumerated as PF BAR4 memory.
PF BAR4 contains AF-PF mbox region followed by its VFs mbox region.
AF-PF mbox region base address is configured at RVU_AF_PFX_BAR4_ADDR
PF-VF mailbox base address is configured at
RVU_PF(x)_VF_MBOX_ADDR = RVU_AF_PF()_BAR4_ADDR+64KB. PF access its
mbox region via BAR4, whereas VF accesses PF-VF DRAM mailboxes via
BAR2 indirect access.

On CN9XX platform:
Mailbox region in DRAM is divided into two parts AF-PF mbox region and
PF-VF mbox region i.e all PFs mbox region is contiguous similarly all
VFs.
The base address of the AF-PF mbox region is configured at
RVU_AF_PF_BAR4_ADDR.
AF-PF1 mbox address can be calculated as RVU_AF_PF_BAR4_ADDR * mbox
size.

This patch changes mbox initialization to support both CN9XX and CN10K
platform.
This patch also removes platform specific name from the PF/VF driver name
to make it appropriate for all supported platforms.

Signed-off-by: default avatarSrujana Challa <schalla@marvell.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 76f24b4f

drivers/crypto/marvell/octeontx2/Makefile

+6 −6
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only

obj-$(CONFIG_CRYPTO_DEV_OCTEONTX2_CPT) += octeontx2-cpt.o octeontx2-cptvf.o

obj-$(CONFIG_CRYPTO_DEV_OCTEONTX2_CPT) += rvu_cptpf.o rvu_cptvf.o



octeontx2-cpt-objs := otx2_cptpf_main.o otx2_cptpf_mbox.o \

rvu_cptpf-objs := otx2_cptpf_main.o otx2_cptpf_mbox.o \

		  otx2_cpt_mbox_common.o otx2_cptpf_ucode.o otx2_cptlf.o

octeontx2-cptvf-objs := otx2_cptvf_main.o otx2_cptvf_mbox.o otx2_cptlf.o \

rvu_cptvf-objs := otx2_cptvf_main.o otx2_cptvf_mbox.o otx2_cptlf.o \

		  otx2_cpt_mbox_common.o otx2_cptvf_reqmgr.o \

		  otx2_cptvf_algs.o

drivers/crypto/marvell/octeontx2/otx2_cpt_common.h

+20 −0
Original line number Diff line number Diff line
@@ -25,6 +25,9 @@ 
#define OTX2_CPT_NAME_LENGTH 64

#define OTX2_CPT_DMA_MINALIGN 128



/* HW capability flags */

#define CN10K_MBOX  0



#define BAD_OTX2_CPT_ENG_TYPE OTX2_CPT_MAX_ENG_TYPES



enum otx2_cpt_eng_type {
@@ -116,6 +119,23 @@ static inline u64 otx2_cpt_read64(void __iomem *reg_base, u64 blk, u64 slot, 
			     OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs));

}



static inline bool is_dev_otx2(struct pci_dev *pdev)

{

	if (pdev->device == OTX2_CPT_PCI_PF_DEVICE_ID ||

	    pdev->device == OTX2_CPT_PCI_VF_DEVICE_ID)

		return true;



	return false;

}



static inline void otx2_cpt_set_hw_caps(struct pci_dev *pdev,

					unsigned long *cap_flag)

{

	if (!is_dev_otx2(pdev))

		__set_bit(CN10K_MBOX, cap_flag);

}





int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);

int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);

drivers/crypto/marvell/octeontx2/otx2_cpt_hw_types.h

+3 −0
Original line number Diff line number Diff line
@@ -10,6 +10,8 @@ 
/* Device IDs */

#define OTX2_CPT_PCI_PF_DEVICE_ID 0xA0FD

#define OTX2_CPT_PCI_VF_DEVICE_ID 0xA0FE

#define CN10K_CPT_PCI_PF_DEVICE_ID 0xA0F2

#define CN10K_CPT_PCI_VF_DEVICE_ID 0xA0F3



/* Mailbox interrupts offset */

#define OTX2_CPT_PF_MBOX_INT	6
@@ -25,6 +27,7 @@ 
 */

#define OTX2_CPT_VF_MSIX_VECTORS 1

#define OTX2_CPT_VF_INTR_MBOX_MASK BIT(0)

#define CN10K_CPT_VF_MBOX_REGION  (0xC0000)



/* CPT LF MSIX vectors */

#define OTX2_CPT_LF_MSIX_VECTORS 2

drivers/crypto/marvell/octeontx2/otx2_cptpf.h

+1 −0
Original line number Diff line number Diff line
@@ -47,6 +47,7 @@ struct otx2_cptpf_dev { 
	struct workqueue_struct	*flr_wq;

	struct cptpf_flr_work   *flr_work;



	unsigned long cap_flag;

	u8 pf_id;               /* RVU PF number */

	u8 max_vfs;		/* Maximum number of VFs supported by CPT */

	u8 enabled_vfs;		/* Number of enabled VFs */

drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c

+21 −14
Original line number Diff line number Diff line
@@ -8,8 +8,8 @@ 
#include "otx2_cptpf.h"

#include "rvu_reg.h"



#define OTX2_CPT_DRV_NAME    "octeontx2-cpt"

#define OTX2_CPT_DRV_STRING  "Marvell OcteonTX2 CPT Physical Function Driver"

#define OTX2_CPT_DRV_NAME    "rvu_cptpf"

#define OTX2_CPT_DRV_STRING  "Marvell RVU CPT Physical Function Driver"



static void cptpf_enable_vfpf_mbox_intr(struct otx2_cptpf_dev *cptpf,

					int num_vfs)
@@ -284,7 +284,11 @@ static int cptpf_vfpf_mbox_init(struct otx2_cptpf_dev *cptpf, int num_vfs) 
		return -ENOMEM;



	/* Map VF-PF mailbox memory */

	if (test_bit(CN10K_MBOX, &cptpf->cap_flag))

		vfpf_mbox_base = readq(cptpf->reg_base + RVU_PF_VF_MBOX_ADDR);

	else

		vfpf_mbox_base = readq(cptpf->reg_base + RVU_PF_VF_BAR4_ADDR);



	if (!vfpf_mbox_base) {

		dev_err(dev, "VF-PF mailbox address not configured\n");

		err = -ENOMEM;
@@ -365,6 +369,8 @@ static int cptpf_register_afpf_mbox_intr(struct otx2_cptpf_dev *cptpf) 


static int cptpf_afpf_mbox_init(struct otx2_cptpf_dev *cptpf)

{

	struct pci_dev *pdev = cptpf->pdev;

	resource_size_t offset;

	int err;



	cptpf->afpf_mbox_wq = alloc_workqueue("cpt_afpf_mailbox",
@@ -373,8 +379,17 @@ static int cptpf_afpf_mbox_init(struct otx2_cptpf_dev *cptpf) 
	if (!cptpf->afpf_mbox_wq)

		return -ENOMEM;



	offset = pci_resource_start(pdev, PCI_MBOX_BAR_NUM);

	/* Map AF-PF mailbox memory */

	cptpf->afpf_mbox_base = devm_ioremap_wc(&pdev->dev, offset, MBOX_SIZE);

	if (!cptpf->afpf_mbox_base) {

		dev_err(&pdev->dev, "Unable to map BAR4\n");

		err = -ENOMEM;

		goto error;

	}



	err = otx2_mbox_init(&cptpf->afpf_mbox, cptpf->afpf_mbox_base,

			     cptpf->pdev, cptpf->reg_base, MBOX_DIR_PFAF, 1);

			     pdev, cptpf->reg_base, MBOX_DIR_PFAF, 1);

	if (err)

		goto error;
@@ -607,7 +622,6 @@ static int otx2_cptpf_probe(struct pci_dev *pdev, 
			    const struct pci_device_id *ent)

{

	struct device *dev = &pdev->dev;

	resource_size_t offset, size;

	struct otx2_cptpf_dev *cptpf;

	int err;
@@ -644,15 +658,6 @@ static int otx2_cptpf_probe(struct pci_dev *pdev, 
	if (err)

		goto clear_drvdata;



	offset = pci_resource_start(pdev, PCI_MBOX_BAR_NUM);

	size = pci_resource_len(pdev, PCI_MBOX_BAR_NUM);

	/* Map AF-PF mailbox memory */

	cptpf->afpf_mbox_base = devm_ioremap_wc(dev, offset, size);

	if (!cptpf->afpf_mbox_base) {

		dev_err(&pdev->dev, "Unable to map BAR4\n");

		err = -ENODEV;

		goto clear_drvdata;

	}

	err = pci_alloc_irq_vectors(pdev, RVU_PF_INT_VEC_CNT,

				    RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX);

	if (err < 0) {
@@ -660,6 +665,7 @@ static int otx2_cptpf_probe(struct pci_dev *pdev, 
			RVU_PF_INT_VEC_CNT);

		goto clear_drvdata;

	}

	otx2_cpt_set_hw_caps(pdev, &cptpf->cap_flag);

	/* Initialize AF-PF mailbox */

	err = cptpf_afpf_mbox_init(cptpf);

	if (err)
@@ -719,6 +725,7 @@ static void otx2_cptpf_remove(struct pci_dev *pdev) 
/* Supported devices */

static const struct pci_device_id otx2_cpt_id_table[] = {

	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, OTX2_CPT_PCI_PF_DEVICE_ID) },

	{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, CN10K_CPT_PCI_PF_DEVICE_ID) },

	{ 0, }  /* end of table */

};