Commit 4cd4b361 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'bnxt_en-Update-for-net-next' 



Michael Chan says:

====================
bnxt_en: Update for net-next.

This patch series adds 2 main features to the bnxt_en driver: 200G
link speed support and FEC support with some refactoring of the
link speed logic.  The firmware interface is updated to have proper
support for these 2 features.  The ethtool preset max channel value
is also adjusted properly to account for XDP and TCs.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents e6221295 4301304b

drivers/net/ethernet/broadcom/bnxt/bnxt.c

+128 −40
Original line number Diff line number Diff line
@@ -5343,13 +5343,16 @@ static int bnxt_hwrm_vnic_qcaps(struct bnxt *bp) 
		 * VLAN_STRIP_CAP properly.

		 */

		if ((flags & VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP) ||

		    ((bp->flags & BNXT_FLAG_CHIP_P5) &&

		    (BNXT_CHIP_P5_THOR(bp) &&

		     !(bp->fw_cap & BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED)))

			bp->fw_cap |= BNXT_FW_CAP_VLAN_RX_STRIP;

		bp->max_tpa_v2 = le16_to_cpu(resp->max_aggs_supported);

		if (bp->max_tpa_v2)

			bp->hw_ring_stats_size =

				sizeof(struct ctx_hw_stats_ext);

		if (bp->max_tpa_v2) {

			if (BNXT_CHIP_P5_THOR(bp))

				bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5;

			else

				bp->hw_ring_stats_size = BNXT_RING_STATS_SIZE_P5_SR2;

		}

	}

	mutex_unlock(&bp->hwrm_cmd_lock);

	return rc;
@@ -8734,6 +8737,30 @@ void bnxt_tx_enable(struct bnxt *bp) 
		netif_carrier_on(bp->dev);

}



static char *bnxt_report_fec(struct bnxt_link_info *link_info)

{

	u8 active_fec = link_info->active_fec_sig_mode &

			PORT_PHY_QCFG_RESP_ACTIVE_FEC_MASK;



	switch (active_fec) {

	default:

	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_NONE_ACTIVE:

		return "None";

	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE74_ACTIVE:

		return "Clause 74 BaseR";

	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_CLAUSE91_ACTIVE:

		return "Clause 91 RS(528,514)";

	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_1XN_ACTIVE:

		return "Clause 91 RS544_1XN";

	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS544_IEEE_ACTIVE:

		return "Clause 91 RS(544,514)";

	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_1XN_ACTIVE:

		return "Clause 91 RS272_1XN";

	case PORT_PHY_QCFG_RESP_ACTIVE_FEC_FEC_RS272_IEEE_ACTIVE:

		return "Clause 91 RS(272,257)";

	}

}



static void bnxt_report_link(struct bnxt *bp)

{

	if (bp->link_info.link_up) {
@@ -8764,16 +8791,25 @@ static void bnxt_report_link(struct bnxt *bp) 
							 "not active");

		fec = bp->link_info.fec_cfg;

		if (!(fec & PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED))

			netdev_info(bp->dev, "FEC autoneg %s encodings: %s\n",

			netdev_info(bp->dev, "FEC autoneg %s encoding: %s\n",

				    (fec & BNXT_FEC_AUTONEG) ? "on" : "off",

				    (fec & BNXT_FEC_ENC_BASE_R) ? "BaseR" :

				     (fec & BNXT_FEC_ENC_RS) ? "RS" : "None");

				    bnxt_report_fec(&bp->link_info));

	} else {

		netif_carrier_off(bp->dev);

		netdev_err(bp->dev, "NIC Link is Down\n");

	}

}



static bool bnxt_phy_qcaps_no_speed(struct hwrm_port_phy_qcaps_output *resp)

{

	if (!resp->supported_speeds_auto_mode &&

	    !resp->supported_speeds_force_mode &&

	    !resp->supported_pam4_speeds_auto_mode &&

	    !resp->supported_pam4_speeds_force_mode)

		return true;

	return false;

}



static int bnxt_hwrm_phy_qcaps(struct bnxt *bp)

{

	int rc = 0;
@@ -8821,9 +8857,24 @@ static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) 
	if (resp->flags & PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET)

		bp->fw_cap |= BNXT_FW_CAP_PORT_STATS_NO_RESET;



	if (bp->hwrm_spec_code >= 0x10a01) {

		if (bnxt_phy_qcaps_no_speed(resp)) {

			link_info->phy_state = BNXT_PHY_STATE_DISABLED;

			netdev_warn(bp->dev, "Ethernet link disabled\n");

		} else if (link_info->phy_state == BNXT_PHY_STATE_DISABLED) {

			link_info->phy_state = BNXT_PHY_STATE_ENABLED;

			netdev_info(bp->dev, "Ethernet link enabled\n");

			/* Phy re-enabled, reprobe the speeds */

			link_info->support_auto_speeds = 0;

			link_info->support_pam4_auto_speeds = 0;

		}

	}

	if (resp->supported_speeds_auto_mode)

		link_info->support_auto_speeds =

			le16_to_cpu(resp->supported_speeds_auto_mode);

	if (resp->supported_pam4_speeds_auto_mode)

		link_info->support_pam4_auto_speeds =

			le16_to_cpu(resp->supported_pam4_speeds_auto_mode);



	bp->port_count = resp->port_cnt;
@@ -8832,14 +8883,21 @@ static int bnxt_hwrm_phy_qcaps(struct bnxt *bp) 
	return rc;

}



static int bnxt_update_link(struct bnxt *bp, bool chng_link_state)

static bool bnxt_support_dropped(u16 advertising, u16 supported)

{

	u16 diff = advertising ^ supported;



	return ((supported | diff) != supported);

}



int bnxt_update_link(struct bnxt *bp, bool chng_link_state)

{

	int rc = 0;

	struct bnxt_link_info *link_info = &bp->link_info;

	struct hwrm_port_phy_qcfg_input req = {0};

	struct hwrm_port_phy_qcfg_output *resp = bp->hwrm_cmd_resp_addr;

	u8 link_up = link_info->link_up;

	u16 diff;

	bool support_changed = false;



	bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_PORT_PHY_QCFG, -1, -1);
@@ -8866,10 +8924,17 @@ static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) 
	else

		link_info->link_speed = 0;

	link_info->force_link_speed = le16_to_cpu(resp->force_link_speed);

	link_info->force_pam4_link_speed =

		le16_to_cpu(resp->force_pam4_link_speed);

	link_info->support_speeds = le16_to_cpu(resp->support_speeds);

	link_info->support_pam4_speeds = le16_to_cpu(resp->support_pam4_speeds);

	link_info->auto_link_speeds = le16_to_cpu(resp->auto_link_speed_mask);

	link_info->auto_pam4_link_speeds =

		le16_to_cpu(resp->auto_pam4_link_speed_mask);

	link_info->lp_auto_link_speeds =

		le16_to_cpu(resp->link_partner_adv_speeds);

	link_info->lp_auto_pam4_link_speeds =

		resp->link_partner_pam4_adv_speeds;

	link_info->preemphasis = le32_to_cpu(resp->preemphasis);

	link_info->phy_ver[0] = resp->phy_maj;

	link_info->phy_ver[1] = resp->phy_min;
@@ -8918,9 +8983,10 @@ static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) 
	}



	link_info->fec_cfg = PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED;

	if (bp->hwrm_spec_code >= 0x10504)

	if (bp->hwrm_spec_code >= 0x10504) {

		link_info->fec_cfg = le16_to_cpu(resp->fec_cfg);



		link_info->active_fec_sig_mode = resp->active_fec_signal_mode;

	}

	/* TODO: need to add more logic to report VF link */

	if (chng_link_state) {

		if (link_info->phy_link_status == BNXT_LINK_LINK)
@@ -8938,17 +9004,21 @@ static int bnxt_update_link(struct bnxt *bp, bool chng_link_state) 
	if (!BNXT_PHY_CFG_ABLE(bp))

		return 0;



	diff = link_info->support_auto_speeds ^ link_info->advertising;

	if ((link_info->support_auto_speeds | diff) !=

	    link_info->support_auto_speeds) {

		/* An advertised speed is no longer supported, so we need to

		 * update the advertisement settings.  Caller holds RTNL

		 * so we can modify link settings.

	/* Check if any advertised speeds are no longer supported. The caller

	 * holds the link_lock mutex, so we can modify link_info settings.

	 */

	if (bnxt_support_dropped(link_info->advertising,

				 link_info->support_auto_speeds)) {

		link_info->advertising = link_info->support_auto_speeds;

		if (link_info->autoneg & BNXT_AUTONEG_SPEED)

			bnxt_hwrm_set_link_setting(bp, true, false);

		support_changed = true;

	}

	if (bnxt_support_dropped(link_info->advertising_pam4,

				 link_info->support_pam4_auto_speeds)) {

		link_info->advertising_pam4 = link_info->support_pam4_auto_speeds;

		support_changed = true;

	}

	if (support_changed && (link_info->autoneg & BNXT_AUTONEG_SPEED))

		bnxt_hwrm_set_link_setting(bp, true, false);

	return 0;

}
@@ -9007,27 +9077,30 @@ bnxt_hwrm_set_pause_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req) 
	}

}



static void bnxt_hwrm_set_link_common(struct bnxt *bp,

				      struct hwrm_port_phy_cfg_input *req)

static void bnxt_hwrm_set_link_common(struct bnxt *bp, struct hwrm_port_phy_cfg_input *req)

{

	u8 autoneg = bp->link_info.autoneg;

	u16 fw_link_speed = bp->link_info.req_link_speed;

	u16 advertising = bp->link_info.advertising;



	if (autoneg & BNXT_AUTONEG_SPEED) {

		req->auto_mode |=

			PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;



		req->enables |= cpu_to_le32(

			PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);

		req->auto_link_speed_mask = cpu_to_le16(advertising);



	if (bp->link_info.autoneg & BNXT_AUTONEG_SPEED) {

		req->auto_mode |= PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK;

		if (bp->link_info.advertising) {

			req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK);

			req->auto_link_speed_mask = cpu_to_le16(bp->link_info.advertising);

		}

		if (bp->link_info.advertising_pam4) {

			req->enables |=

				cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAM4_LINK_SPEED_MASK);

			req->auto_link_pam4_speed_mask =

				cpu_to_le16(bp->link_info.advertising_pam4);

		}

		req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE);

		req->flags |=

			cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);

		req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG);

	} else {

		req->force_link_speed = cpu_to_le16(fw_link_speed);

		req->flags |= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE);

		if (bp->link_info.req_signal_mode == BNXT_SIG_MODE_PAM4) {

			req->force_pam4_link_speed = cpu_to_le16(bp->link_info.req_link_speed);

			req->enables |= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAM4_LINK_SPEED);

		} else {

			req->force_link_speed = cpu_to_le16(bp->link_info.req_link_speed);

		}

	}



	/* tell chimp that the setting takes effect immediately */
@@ -9423,14 +9496,19 @@ static int bnxt_update_phy_setting(struct bnxt *bp) 
	if (!(link_info->autoneg & BNXT_AUTONEG_SPEED)) {

		if (BNXT_AUTO_MODE(link_info->auto_mode))

			update_link = true;

		if (link_info->req_link_speed != link_info->force_link_speed)

		if (link_info->req_signal_mode == BNXT_SIG_MODE_NRZ &&

		    link_info->req_link_speed != link_info->force_link_speed)

			update_link = true;

		else if (link_info->req_signal_mode == BNXT_SIG_MODE_PAM4 &&

			 link_info->req_link_speed != link_info->force_pam4_link_speed)

			update_link = true;

		if (link_info->req_duplex != link_info->duplex_setting)

			update_link = true;

	} else {

		if (link_info->auto_mode == BNXT_LINK_AUTO_NONE)

			update_link = true;

		if (link_info->advertising != link_info->auto_link_speeds)

		if (link_info->advertising != link_info->auto_link_speeds ||

		    link_info->advertising_pam4 != link_info->auto_pam4_link_speeds)

			update_link = true;

	}
@@ -10690,8 +10768,15 @@ static void bnxt_init_ethtool_link_settings(struct bnxt *bp) 
			link_info->autoneg |= BNXT_AUTONEG_FLOW_CTRL;

		}

		link_info->advertising = link_info->auto_link_speeds;

		link_info->advertising_pam4 = link_info->auto_pam4_link_speeds;

	} else {

		link_info->req_link_speed = link_info->force_link_speed;

		link_info->req_signal_mode = BNXT_SIG_MODE_NRZ;

		if (link_info->force_pam4_link_speed) {

			link_info->req_link_speed =

				link_info->force_pam4_link_speed;

			link_info->req_signal_mode = BNXT_SIG_MODE_PAM4;

		}

		link_info->req_duplex = link_info->duplex_setting;

	}

	if (link_info->autoneg & BNXT_AUTONEG_FLOW_CTRL)
@@ -12233,8 +12318,11 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 
	if (rc)

		goto init_err_pci_clean;



	if (BNXT_CHIP_P5(bp))

	if (BNXT_CHIP_P5(bp)) {

		bp->flags |= BNXT_FLAG_CHIP_P5;

		if (BNXT_CHIP_SR2(bp))

			bp->flags |= BNXT_FLAG_CHIP_SR2;

	}



	rc = bnxt_alloc_rss_indir_tbl(bp);

	if (rc)

drivers/net/ethernet/broadcom/bnxt/bnxt.h

+105 −50
Original line number Diff line number Diff line
@@ -1142,50 +1142,6 @@ struct bnxt_ntuple_filter { 
#define BNXT_FLTR_UPDATE	1

};



struct hwrm_port_phy_qcfg_output_compat {

	__le16	error_code;

	__le16	req_type;

	__le16	seq_id;

	__le16	resp_len;

	u8	link;

	u8	link_signal_mode;

	__le16	link_speed;

	u8	duplex_cfg;

	u8	pause;

	__le16	support_speeds;

	__le16	force_link_speed;

	u8	auto_mode;

	u8	auto_pause;

	__le16	auto_link_speed;

	__le16	auto_link_speed_mask;

	u8	wirespeed;

	u8	lpbk;

	u8	force_pause;

	u8	module_status;

	__le32	preemphasis;

	u8	phy_maj;

	u8	phy_min;

	u8	phy_bld;

	u8	phy_type;

	u8	media_type;

	u8	xcvr_pkg_type;

	u8	eee_config_phy_addr;

	u8	parallel_detect;

	__le16	link_partner_adv_speeds;

	u8	link_partner_adv_auto_mode;

	u8	link_partner_adv_pause;

	__le16	adv_eee_link_speed_mask;

	__le16	link_partner_adv_eee_link_speed_mask;

	__le32	xcvr_identifier_type_tx_lpi_timer;

	__le16	fec_cfg;

	u8	duplex_state;

	u8	option_flags;

	char	phy_vendor_name[16];

	char	phy_vendor_partnumber[16];

	u8	unused_0[7];

	u8	valid;

};



struct bnxt_link_info {

	u8			phy_type;

	u8			media_type;
@@ -1196,7 +1152,10 @@ struct bnxt_link_info { 
#define BNXT_LINK_SIGNAL	PORT_PHY_QCFG_RESP_LINK_SIGNAL

#define BNXT_LINK_LINK		PORT_PHY_QCFG_RESP_LINK_LINK

	u8			wire_speed;

	u8			loop_back;

	u8			phy_state;

#define BNXT_PHY_STATE_ENABLED		0

#define BNXT_PHY_STATE_DISABLED		1



	u8			link_up;

	u8			duplex;

#define BNXT_LINK_DUPLEX_HALF	PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
@@ -1232,6 +1191,7 @@ struct bnxt_link_info { 
#define BNXT_LINK_SPEED_50GB	PORT_PHY_QCFG_RESP_LINK_SPEED_50GB

#define BNXT_LINK_SPEED_100GB	PORT_PHY_QCFG_RESP_LINK_SPEED_100GB

	u16			support_speeds;

	u16			support_pam4_speeds;

	u16			auto_link_speeds;	/* fw adv setting */

#define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB

#define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
@@ -1243,24 +1203,51 @@ struct bnxt_link_info { 
#define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB

#define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB

#define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB

	u16			auto_pam4_link_speeds;

#define BNXT_LINK_PAM4_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_50G

#define BNXT_LINK_PAM4_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_100G

#define BNXT_LINK_PAM4_SPEED_MSK_200GB PORT_PHY_QCFG_RESP_SUPPORT_PAM4_SPEEDS_200G

	u16			support_auto_speeds;

	u16			support_pam4_auto_speeds;

	u16			lp_auto_link_speeds;

	u16			lp_auto_pam4_link_speeds;

	u16			force_link_speed;

	u16			force_pam4_link_speed;

	u32			preemphasis;

	u8			module_status;

	u8			active_fec_sig_mode;

	u16			fec_cfg;

#define BNXT_FEC_NONE		PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED

#define BNXT_FEC_AUTONEG_CAP	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED

#define BNXT_FEC_AUTONEG	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED

#define BNXT_FEC_ENC_BASE_R_CAP	\

	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED

#define BNXT_FEC_ENC_BASE_R	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED

#define BNXT_FEC_ENC_RS		PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED

#define BNXT_FEC_ENC_RS_CAP	\

	PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED

#define BNXT_FEC_ENC_LLRS_CAP	\

	(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_SUPPORTED |	\

	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_SUPPORTED)

#define BNXT_FEC_ENC_RS		\

	(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED |	\

	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_1XN_ENABLED |	\

	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS544_IEEE_ENABLED)

#define BNXT_FEC_ENC_LLRS	\

	(PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_1XN_ENABLED |	\

	 PORT_PHY_QCFG_RESP_FEC_CFG_FEC_RS272_IEEE_ENABLED)



	/* copy of requested setting from ethtool cmd */

	u8			autoneg;

#define BNXT_AUTONEG_SPEED		1

#define BNXT_AUTONEG_FLOW_CTRL		2

	u8			req_signal_mode;

#define BNXT_SIG_MODE_NRZ	PORT_PHY_QCFG_RESP_SIGNAL_MODE_NRZ

#define BNXT_SIG_MODE_PAM4	PORT_PHY_QCFG_RESP_SIGNAL_MODE_PAM4

	u8			req_duplex;

	u8			req_flow_ctrl;

	u16			req_link_speed;

	u16			advertising;	/* user adv setting */

	u16			advertising_pam4;

	bool			force_link_chng;



	bool			phy_retry;
@@ -1272,6 +1259,49 @@ struct bnxt_link_info { 
	struct hwrm_port_phy_qcfg_output phy_qcfg_resp;

};



#define BNXT_FEC_RS544_ON					\

	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_ENABLE |		\

	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_ENABLE)



#define BNXT_FEC_RS544_OFF					\

	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_1XN_DISABLE |	\

	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS544_IEEE_DISABLE)



#define BNXT_FEC_RS272_ON					\

	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_ENABLE |		\

	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_ENABLE)



#define BNXT_FEC_RS272_OFF					\

	 (PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_1XN_DISABLE |	\

	  PORT_PHY_CFG_REQ_FLAGS_FEC_RS272_IEEE_DISABLE)



#define BNXT_PAM4_SUPPORTED(link_info)				\

	((link_info)->support_pam4_speeds)



#define BNXT_FEC_RS_ON(link_info)				\

	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |		\

	 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |		\

	 (BNXT_PAM4_SUPPORTED(link_info) ?			\

	  (BNXT_FEC_RS544_ON | BNXT_FEC_RS272_OFF) : 0))



#define BNXT_FEC_LLRS_ON					\

	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE |		\

	 PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |		\

	 BNXT_FEC_RS272_ON | BNXT_FEC_RS544_OFF)



#define BNXT_FEC_RS_OFF(link_info)				\

	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE |		\

	 (BNXT_PAM4_SUPPORTED(link_info) ?			\

	  (BNXT_FEC_RS544_OFF | BNXT_FEC_RS272_OFF) : 0))



#define BNXT_FEC_BASE_R_ON(link_info)				\

	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE |		\

	 BNXT_FEC_RS_OFF(link_info))



#define BNXT_FEC_ALL_OFF(link_info)				\

	(PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE |		\

	 BNXT_FEC_RS_OFF(link_info))



#define BNXT_MAX_QUEUE	8



struct bnxt_queue_info {
@@ -1535,6 +1565,8 @@ struct bnxt { 


	u8			chip_rev;



#define CHIP_NUM_58818		0xd818



#define BNXT_CHIP_NUM_5730X(chip_num)		\

	((chip_num) >= CHIP_NUM_57301 &&	\

	 (chip_num) <= CHIP_NUM_57304)
@@ -1613,6 +1645,7 @@ struct bnxt { 
					 BNXT_FLAG_ROCEV2_CAP)

	#define BNXT_FLAG_NO_AGG_RINGS	0x20000

	#define BNXT_FLAG_RX_PAGE_MODE	0x40000

	#define BNXT_FLAG_CHIP_SR2	0x80000

	#define BNXT_FLAG_MULTI_HOST	0x100000

	#define BNXT_FLAG_DSN_VALID	0x200000

	#define BNXT_FLAG_DOUBLE_DB	0x400000
@@ -1630,20 +1663,27 @@ struct bnxt { 
#define BNXT_NPAR(bp)		((bp)->port_partition_type)

#define BNXT_MH(bp)		((bp)->flags & BNXT_FLAG_MULTI_HOST)

#define BNXT_SINGLE_PF(bp)	(BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))

#define BNXT_PHY_CFG_ABLE(bp)	(BNXT_SINGLE_PF(bp) ||			\

				 ((bp)->fw_cap & BNXT_FW_CAP_SHARED_PORT_CFG))

#define BNXT_PHY_CFG_ABLE(bp)	((BNXT_SINGLE_PF(bp) ||			\

				  ((bp)->fw_cap & BNXT_FW_CAP_SHARED_PORT_CFG)) && \

				 (bp)->link_info.phy_state == BNXT_PHY_STATE_ENABLED)

#define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)

#define BNXT_RX_PAGE_MODE(bp)	((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)

#define BNXT_SUPPORTS_TPA(bp)	(!BNXT_CHIP_TYPE_NITRO_A0(bp) &&	\

				 (!((bp)->flags & BNXT_FLAG_CHIP_P5) ||	\

				  (bp)->max_tpa_v2) && !is_kdump_kernel())



/* Chip class phase 5 */

#define BNXT_CHIP_P5(bp)			\

#define BNXT_CHIP_SR2(bp)			\

	((bp)->chip_num == CHIP_NUM_58818)



#define BNXT_CHIP_P5_THOR(bp)			\

	((bp)->chip_num == CHIP_NUM_57508 ||	\

	 (bp)->chip_num == CHIP_NUM_57504 ||	\

	 (bp)->chip_num == CHIP_NUM_57502)



/* Chip class phase 5 */

#define BNXT_CHIP_P5(bp)			\

	(BNXT_CHIP_P5_THOR(bp) || BNXT_CHIP_SR2(bp))



/* Chip class phase 4.x */

#define BNXT_CHIP_P4(bp)			\

	(BNXT_CHIP_NUM_57X1X((bp)->chip_num) ||	\
@@ -1935,6 +1975,20 @@ struct bnxt { 
	struct device		*hwmon_dev;

};



#define BNXT_NUM_RX_RING_STATS			8

#define BNXT_NUM_TX_RING_STATS			8

#define BNXT_NUM_TPA_RING_STATS			4

#define BNXT_NUM_TPA_RING_STATS_P5		5

#define BNXT_NUM_TPA_RING_STATS_P5_SR2		6



#define BNXT_RING_STATS_SIZE_P5					\

	((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +	\

	  BNXT_NUM_TPA_RING_STATS_P5) * 8)



#define BNXT_RING_STATS_SIZE_P5_SR2				\

	((BNXT_NUM_RX_RING_STATS + BNXT_NUM_TX_RING_STATS +	\

	  BNXT_NUM_TPA_RING_STATS_P5_SR2) * 8)



#define BNXT_GET_RING_STATS64(sw, counter)		\

	(*((sw) + offsetof(struct ctx_hw_stats, counter) / 8))
@@ -2114,6 +2168,7 @@ int bnxt_get_avail_msix(struct bnxt *bp, int num); 
int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);

void bnxt_tx_disable(struct bnxt *bp);

void bnxt_tx_enable(struct bnxt *bp);

int bnxt_update_link(struct bnxt *bp, bool chng_link_state);

int bnxt_hwrm_set_pause(struct bnxt *);

int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);

int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);

drivers/net/ethernet/broadcom/bnxt/bnxt_ethtool.c

+259 −35

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h

+317 −58

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/broadcom/bnxt/bnxt_sriov.c

+1 −1
Original line number Diff line number Diff line
@@ -1029,7 +1029,7 @@ static int bnxt_vf_set_link(struct bnxt *bp, struct bnxt_vf_info *vf) 
		rc = bnxt_hwrm_exec_fwd_resp(

			bp, vf, sizeof(struct hwrm_port_phy_qcfg_input));

	} else {

		struct hwrm_port_phy_qcfg_output_compat phy_qcfg_resp = {0};

		struct hwrm_port_phy_qcfg_output phy_qcfg_resp = {0};

		struct hwrm_port_phy_qcfg_input *phy_qcfg_req;



		phy_qcfg_req =