Commit 4cc9f86f authored by Tom St Denis's avatar Tom St Denis Committed by Alex Deucher
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drm/amd/amdgpu: Add pcie indirect support to amdgpu_mm_wreg_mmio_rlc() 



The function amdgpu_mm_wreg_mmio_rlc() is used by debugfs to write to
MMIO registers.  It didn't support registers beyond the BAR mapped MMIO
space.  This adds pcie indirect write support.

Signed-off-by: default avatarTom St Denis <tom.stdenis@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 575e55ee

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+3 −1
Original line number Diff line number Diff line
@@ -552,7 +552,7 @@ void amdgpu_device_wreg(struct amdgpu_device *adev, 
}



/**

 * amdgpu_mm_wreg_mmio_rlc -  write register either with mmio or with RLC path if in range

 * amdgpu_mm_wreg_mmio_rlc -  write register either with direct/indirect mmio or with RLC path if in range

 *

 * this function is invoked only the debugfs register access

 */
@@ -567,6 +567,8 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 
	    adev->gfx.rlc.funcs->is_rlcg_access_range) {

		if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))

			return adev->gfx.rlc.funcs->sriov_wreg(adev, reg, v, 0, 0);

	} else if ((reg * 4) >= adev->rmmio_size) {

		adev->pcie_wreg(adev, reg * 4, v);

	} else {

		writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));

	}