Commit 4cb50d00 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'mv88e6393x' 



Marek Behún says:

====================
Add support for mv88e6393x family of Marvell

after 2 months I finally had time to send v17 of Amethyst patches.

This series is tested on Marvell CN9130-CRB.

Changes since v16:
- dropped patches adding 5gbase-r, since they are already merged
- rebased onto net-next/master
- driver API renamed set_egress_flood() method into 2 methods for
  ucast/mcast floods, so this is fixed

Changes from v15:
- put 10000baseKR_Full back into phylink_validate method for Amethyst,
  it seems I misunderstood the meaning behind things and removed it
  from v15
- removed erratum 3.7, since the procedure is done anyway in
  mv88e6390_serdes_pcs_config
- renumbered errata 3.6 and 3.8 to 4.6 and 4.8, according to newer
  version of the errata document
- refactored errata code a little and removed duplicate macro
  definitions (for example MV88E6390_SGMII_CONTROL is already called
  MV88E6390_SGMII_BMCR)

Changes from v14:
- added my Signed-off-by tags to Pavana's patches, since I am sending
  them (as suggested by Andrew)
- added documentation to second patch adding 5gbase-r mode (as requested
  by Russell)
- added Reviewed-by tags
- applied Vladimir's suggestions:
  - reduced indentation level in mv88e6xxx_set_egress_port and
    mv88e6393x_serdes_port_config
  - removed 10000baseKR_Full from mv88e6393x_phylink_validate
  - removed PHY_INTERFACE_MODE_10GKR from mv88e6xxx_port_set_cmode

Changes from v13:
- added patch that wraps .set_egress_port into mv88e6xxx_set_egress_port,
  so that we do not have to set chip->*gress_dest_port members in every
  implementation of this method
- for the patch that adds Amethyst support:
  - added more information into commit message
  - added these methods for mv88e6393x_ops:
      .port_sync_link
      .port_setup_message_port
      .port_max_speed_mode (new implementation needed)
      .atu_get_hash
      .atu_set_hash
      .serdes_pcs_config
      .serdes_pcs_an_restart
      .serdes_pcs_link_up
  - this device can set upstream port per port, so implement
      .port_set_upstream_port
    instead of
      .set_cpu_port
  - removed USXGMII cmode (not yet supported, working on it)
  - added debug messages into mv88e6393x_port_set_speed_duplex
  - added Amethyst errata 4.5 (EEE should be disabled on SERDES ports)
  - fixed 5gbase-r serdes configuration and interrupt handling
  - refactored mv88e6393x_serdes_setup_errata
  - refactored mv88e6393x_port_policy_write
- added patch implementing .port_set_policy for Amethyst
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents ac1bbf8a 6584b260

drivers/net/dsa/mv88e6xxx/chip.c

+201 −32
Original line number Diff line number Diff line
@@ -485,12 +485,12 @@ static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 
					  struct phylink_link_state *state)

{

	struct mv88e6xxx_chip *chip = ds->priv;

	u8 lane;

	int lane;

	int err;



	mv88e6xxx_reg_lock(chip);

	lane = mv88e6xxx_serdes_get_lane(chip, port);

	if (lane && chip->info->ops->serdes_pcs_get_state)

	if (lane >= 0 && chip->info->ops->serdes_pcs_get_state)

		err = chip->info->ops->serdes_pcs_get_state(chip, port, lane,

							    state);

	else
@@ -506,11 +506,11 @@ static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 
				       const unsigned long *advertise)

{

	const struct mv88e6xxx_ops *ops = chip->info->ops;

	u8 lane;

	int lane;



	if (ops->serdes_pcs_config) {

		lane = mv88e6xxx_serdes_get_lane(chip, port);

		if (lane)

		if (lane >= 0)

			return ops->serdes_pcs_config(chip, port, lane, mode,

						      interface, advertise);

	}
@@ -523,14 +523,14 @@ static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 
	struct mv88e6xxx_chip *chip = ds->priv;

	const struct mv88e6xxx_ops *ops;

	int err = 0;

	u8 lane;

	int lane;



	ops = chip->info->ops;



	if (ops->serdes_pcs_an_restart) {

		mv88e6xxx_reg_lock(chip);

		lane = mv88e6xxx_serdes_get_lane(chip, port);

		if (lane)

		if (lane >= 0)

			err = ops->serdes_pcs_an_restart(chip, port, lane);

		mv88e6xxx_reg_unlock(chip);
@@ -544,11 +544,11 @@ static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 
					int speed, int duplex)

{

	const struct mv88e6xxx_ops *ops = chip->info->ops;

	u8 lane;

	int lane;



	if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) {

		lane = mv88e6xxx_serdes_get_lane(chip, port);

		if (lane)

		if (lane >= 0)

			return ops->serdes_pcs_link_up(chip, port, lane,

						       speed, duplex);

	}
@@ -635,6 +635,29 @@ static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 
	mv88e6390_phylink_validate(chip, port, mask, state);

}



static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port,

					unsigned long *mask,

					struct phylink_link_state *state)

{

	if (port == 0 || port == 9 || port == 10) {

		phylink_set(mask, 10000baseT_Full);

		phylink_set(mask, 10000baseKR_Full);

		phylink_set(mask, 10000baseCR_Full);

		phylink_set(mask, 10000baseSR_Full);

		phylink_set(mask, 10000baseLR_Full);

		phylink_set(mask, 10000baseLRM_Full);

		phylink_set(mask, 10000baseER_Full);

		phylink_set(mask, 5000baseT_Full);

		phylink_set(mask, 2500baseX_Full);

		phylink_set(mask, 2500baseT_Full);

	}



	phylink_set(mask, 1000baseT_Full);

	phylink_set(mask, 1000baseX_Full);



	mv88e6065_phylink_validate(chip, port, mask, state);

}



static void mv88e6xxx_validate(struct dsa_switch *ds, int port,

			       unsigned long *supported,

			       struct phylink_link_state *state)
@@ -2460,11 +2483,11 @@ static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 
	struct mv88e6xxx_chip *chip = mvp->chip;

	irqreturn_t ret = IRQ_NONE;

	int port = mvp->port;

	u8 lane;

	int lane;



	mv88e6xxx_reg_lock(chip);

	lane = mv88e6xxx_serdes_get_lane(chip, port);

	if (lane)

	if (lane >= 0)

		ret = mv88e6xxx_serdes_irq_status(chip, port, lane);

	mv88e6xxx_reg_unlock(chip);
@@ -2472,7 +2495,7 @@ static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 
}



static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port,

					u8 lane)

					int lane)

{

	struct mv88e6xxx_port *dev_id = &chip->ports[port];

	unsigned int irq;
@@ -2501,7 +2524,7 @@ static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 
}



static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port,

				     u8 lane)

				     int lane)

{

	struct mv88e6xxx_port *dev_id = &chip->ports[port];

	unsigned int irq = dev_id->serdes_irq;
@@ -2526,11 +2549,11 @@ static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 
static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,

				  bool on)

{

	u8 lane;

	int lane;

	int err;



	lane = mv88e6xxx_serdes_get_lane(chip, port);

	if (!lane)

	if (lane < 0)

		return 0;



	if (on) {
@@ -2550,6 +2573,27 @@ static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 
	return err;

}



static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip,

				     enum mv88e6xxx_egress_direction direction,

				     int port)

{

	int err;



	if (!chip->info->ops->set_egress_port)

		return -EOPNOTSUPP;



	err = chip->info->ops->set_egress_port(chip, direction, port);

	if (err)

		return err;



	if (direction == MV88E6XXX_EGRESS_DIR_INGRESS)

		chip->ingress_dest_port = port;

	else

		chip->egress_dest_port = port;



	return 0;

}



static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)

{

	struct dsa_switch *ds = chip->ds;
@@ -2572,20 +2616,18 @@ static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 
				return err;

		}



		if (chip->info->ops->set_egress_port) {

			err = chip->info->ops->set_egress_port(chip,

		err = mv88e6xxx_set_egress_port(chip,

						MV88E6XXX_EGRESS_DIR_INGRESS,

						upstream_port);

			if (err)

		if (err && err != -EOPNOTSUPP)

			return err;



			err = chip->info->ops->set_egress_port(chip,

		err = mv88e6xxx_set_egress_port(chip,

						MV88E6XXX_EGRESS_DIR_EGRESS,

						upstream_port);

			if (err)

		if (err && err != -EOPNOTSUPP)

			return err;

	}

	}



	return 0;

}
@@ -4570,6 +4612,70 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = { 
	.phylink_validate = mv88e6390x_phylink_validate,

};



static const struct mv88e6xxx_ops mv88e6393x_ops = {

	/* MV88E6XXX_FAMILY_6393 */

	.setup_errata = mv88e6393x_serdes_setup_errata,

	.irl_init_all = mv88e6390_g2_irl_init_all,

	.get_eeprom = mv88e6xxx_g2_get_eeprom8,

	.set_eeprom = mv88e6xxx_g2_set_eeprom8,

	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,

	.phy_read = mv88e6xxx_g2_smi_phy_read,

	.phy_write = mv88e6xxx_g2_smi_phy_write,

	.port_set_link = mv88e6xxx_port_set_link,

	.port_sync_link = mv88e6xxx_port_sync_link,

	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,

	.port_set_speed_duplex = mv88e6393x_port_set_speed_duplex,

	.port_max_speed_mode = mv88e6393x_port_max_speed_mode,

	.port_tag_remap = mv88e6390_port_tag_remap,

	.port_set_policy = mv88e6393x_port_set_policy,

	.port_set_frame_mode = mv88e6351_port_set_frame_mode,

	.port_set_ucast_flood = mv88e6352_port_set_ucast_flood,

	.port_set_mcast_flood = mv88e6352_port_set_mcast_flood,

	.port_set_ether_type = mv88e6393x_port_set_ether_type,

	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,

	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,

	.port_pause_limit = mv88e6390_port_pause_limit,

	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,

	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,

	.port_get_cmode = mv88e6352_port_get_cmode,

	.port_set_cmode = mv88e6393x_port_set_cmode,

	.port_setup_message_port = mv88e6xxx_setup_message_port,

	.port_set_upstream_port = mv88e6393x_port_set_upstream_port,

	.stats_snapshot = mv88e6390_g1_stats_snapshot,

	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,

	.stats_get_sset_count = mv88e6320_stats_get_sset_count,

	.stats_get_strings = mv88e6320_stats_get_strings,

	.stats_get_stats = mv88e6390_stats_get_stats,

	/* .set_cpu_port is missing because this family does not support a global

	 * CPU port, only per port CPU port which is set via

	 * .port_set_upstream_port method.

	 */

	.set_egress_port = mv88e6393x_set_egress_port,

	.watchdog_ops = &mv88e6390_watchdog_ops,

	.mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu,

	.pot_clear = mv88e6xxx_g2_pot_clear,

	.reset = mv88e6352_g1_reset,

	.rmu_disable = mv88e6390_g1_rmu_disable,

	.atu_get_hash = mv88e6165_g1_atu_get_hash,

	.atu_set_hash = mv88e6165_g1_atu_set_hash,

	.vtu_getnext = mv88e6390_g1_vtu_getnext,

	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,

	.serdes_power = mv88e6393x_serdes_power,

	.serdes_get_lane = mv88e6393x_serdes_get_lane,

	.serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state,

	.serdes_pcs_config = mv88e6390_serdes_pcs_config,

	.serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart,

	.serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up,

	.serdes_irq_mapping = mv88e6390_serdes_irq_mapping,

	.serdes_irq_enable = mv88e6393x_serdes_irq_enable,

	.serdes_irq_status = mv88e6393x_serdes_irq_status,

	/* TODO: serdes stats */

	.gpio_ops = &mv88e6352_gpio_ops,

	.avb_ops = &mv88e6390_avb_ops,

	.ptp_ops = &mv88e6352_ptp_ops,

	.phylink_validate = mv88e6393x_phylink_validate,

};



static const struct mv88e6xxx_info mv88e6xxx_table[] = {

	[MV88E6085] = {

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
@@ -4941,6 +5047,52 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
		.ops = &mv88e6191_ops,

	},



	[MV88E6191X] = {

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X,

		.family = MV88E6XXX_FAMILY_6393,

		.name = "Marvell 88E6191X",

		.num_databases = 4096,

		.num_ports = 11,	/* 10 + Z80 */

		.num_internal_phys = 9,

		.max_vid = 8191,

		.port_base_addr = 0x0,

		.phy_base_addr = 0x0,

		.global1_addr = 0x1b,

		.global2_addr = 0x1c,

		.age_time_coeff = 3750,

		.g1_irqs = 10,

		.g2_irqs = 14,

		.atu_move_port_mask = 0x1f,

		.pvt = true,

		.multi_chip = true,

		.tag_protocol = DSA_TAG_PROTO_DSA,

		.ptp_support = true,

		.ops = &mv88e6393x_ops,

	},



	[MV88E6193X] = {

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X,

		.family = MV88E6XXX_FAMILY_6393,

		.name = "Marvell 88E6193X",

		.num_databases = 4096,

		.num_ports = 11,	/* 10 + Z80 */

		.num_internal_phys = 9,

		.max_vid = 8191,

		.port_base_addr = 0x0,

		.phy_base_addr = 0x0,

		.global1_addr = 0x1b,

		.global2_addr = 0x1c,

		.age_time_coeff = 3750,

		.g1_irqs = 10,

		.g2_irqs = 14,

		.atu_move_port_mask = 0x1f,

		.pvt = true,

		.multi_chip = true,

		.tag_protocol = DSA_TAG_PROTO_DSA,

		.ptp_support = true,

		.ops = &mv88e6393x_ops,

	},



	[MV88E6220] = {

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220,

		.family = MV88E6XXX_FAMILY_6250,
@@ -5231,6 +5383,29 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = { 
		.ptp_support = true,

		.ops = &mv88e6390x_ops,

	},



	[MV88E6393X] = {

		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X,

		.family = MV88E6XXX_FAMILY_6393,

		.name = "Marvell 88E6393X",

		.num_databases = 4096,

		.num_ports = 11,	/* 10 + Z80 */

		.num_internal_phys = 9,

		.max_vid = 8191,

		.port_base_addr = 0x0,

		.phy_base_addr = 0x0,

		.global1_addr = 0x1b,

		.global2_addr = 0x1c,

		.age_time_coeff = 3750,

		.g1_irqs = 10,

		.g2_irqs = 14,

		.atu_move_port_mask = 0x1f,

		.pvt = true,

		.multi_chip = true,

		.tag_protocol = DSA_TAG_PROTO_DSA,

		.ptp_support = true,

		.ops = &mv88e6393x_ops,

	},

};



static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
@@ -5338,9 +5513,6 @@ static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 
	int i;

	int err;



	if (!chip->info->ops->set_egress_port)

		return -EOPNOTSUPP;



	mutex_lock(&chip->reg_lock);

	if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) !=

	    mirror->to_local_port) {
@@ -5355,8 +5527,7 @@ static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 
			goto out;

		}



		err = chip->info->ops->set_egress_port(chip,

						       direction,

		err = mv88e6xxx_set_egress_port(chip, direction,

						mirror->to_local_port);

		if (err)

			goto out;
@@ -5390,10 +5561,8 @@ static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 


	/* Reset egress port when no other mirror is active */

	if (!other_mirrors) {

		if (chip->info->ops->set_egress_port(chip,

						     direction,

						     dsa_upstream_port(ds,

								       port)))

		if (mv88e6xxx_set_egress_port(chip, direction,

					      dsa_upstream_port(ds, port)))

			dev_err(ds->dev, "failed to set egress port\n");

	}

drivers/net/dsa/mv88e6xxx/chip.h

+12 −8
Original line number Diff line number Diff line
@@ -63,6 +63,8 @@ enum mv88e6xxx_model { 
	MV88E6190,

	MV88E6190X,

	MV88E6191,

	MV88E6191X,

	MV88E6193X,

	MV88E6220,

	MV88E6240,

	MV88E6250,
@@ -75,6 +77,7 @@ enum mv88e6xxx_model { 
	MV88E6352,

	MV88E6390,

	MV88E6390X,

	MV88E6393X,

};



enum mv88e6xxx_family {
@@ -90,6 +93,7 @@ enum mv88e6xxx_family { 
	MV88E6XXX_FAMILY_6351,	/* 6171 6175 6350 6351 */

	MV88E6XXX_FAMILY_6352,	/* 6172 6176 6240 6352 */

	MV88E6XXX_FAMILY_6390,  /* 6190 6190X 6191 6290 6390 6390X */

	MV88E6XXX_FAMILY_6393,	/* 6191X 6193X 6393X */

};



struct mv88e6xxx_ops;
@@ -513,30 +517,30 @@ struct mv88e6xxx_ops { 
	int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);



	/* Power on/off a SERDES interface */

	int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, u8 lane,

	int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, int lane,

			    bool up);



	/* SERDES lane mapping */

	u8 (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);

	int (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);



	int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port,

				    u8 lane, struct phylink_link_state *state);

				    int lane, struct phylink_link_state *state);

	int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port,

				 u8 lane, unsigned int mode,

				 int lane, unsigned int mode,

				 phy_interface_t interface,

				 const unsigned long *advertise);

	int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port,

				     u8 lane);

				     int lane);

	int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port,

				  u8 lane, int speed, int duplex);

				  int lane, int speed, int duplex);



	/* SERDES interrupt handling */

	unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip,

					   int port);

	int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, u8 lane,

	int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, int lane,

				 bool enable);

	irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port,

					 u8 lane);

					 int lane);



	/* Statistics from the SERDES interface */

	int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);

drivers/net/dsa/mv88e6xxx/global1.c

+2 −17
Original line number Diff line number Diff line
@@ -315,7 +315,6 @@ int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, 
				 enum mv88e6xxx_egress_direction direction,

				 int port)

{

	int *dest_port_chip;

	u16 reg;

	int err;
@@ -325,13 +324,11 @@ int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, 


	switch (direction) {

	case MV88E6XXX_EGRESS_DIR_INGRESS:

		dest_port_chip = &chip->ingress_dest_port;

		reg &= ~MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK;

		reg |= port <<

		       __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK);

		break;

	case MV88E6XXX_EGRESS_DIR_EGRESS:

		dest_port_chip = &chip->egress_dest_port;

		reg &= ~MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK;

		reg |= port <<

		       __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
@@ -340,11 +337,7 @@ int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip, 
		return -EINVAL;

	}



	err = mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);

	if (!err)

		*dest_port_chip = port;



	return err;

	return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);

}



/* Older generations also call this the ARP destination. It has been
@@ -380,28 +373,20 @@ int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip, 
				 enum mv88e6xxx_egress_direction direction,

				 int port)

{

	int *dest_port_chip;

	u16 ptr;

	int err;



	switch (direction) {

	case MV88E6XXX_EGRESS_DIR_INGRESS:

		dest_port_chip = &chip->ingress_dest_port;

		ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;

		break;

	case MV88E6XXX_EGRESS_DIR_EGRESS:

		dest_port_chip = &chip->egress_dest_port;

		ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;

		break;

	default:

		return -EINVAL;

	}



	err = mv88e6390_g1_monitor_write(chip, ptr, port);

	if (!err)

		*dest_port_chip = port;



	return err;

	return mv88e6390_g1_monitor_write(chip, ptr, port);

}



int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)

drivers/net/dsa/mv88e6xxx/global1.h

+2 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
#define MV88E6185_G1_STS_PPU_STATE_DISABLED		0x8000

#define MV88E6185_G1_STS_PPU_STATE_POLLING		0xc000

#define MV88E6XXX_G1_STS_INIT_READY			0x0800

#define MV88E6393X_G1_STS_IRQ_DEVICE_2			9

#define MV88E6XXX_G1_STS_IRQ_AVB			8

#define MV88E6XXX_G1_STS_IRQ_DEVICE			7

#define MV88E6XXX_G1_STS_IRQ_STATS			6
@@ -59,6 +60,7 @@ 
#define MV88E6185_G1_CTL1_SCHED_PRIO		0x0800

#define MV88E6185_G1_CTL1_MAX_FRAME_1632	0x0400

#define MV88E6185_G1_CTL1_RELOAD_EEPROM		0x0200

#define MV88E6393X_G1_CTL1_DEVICE2_EN		0x0200

#define MV88E6XXX_G1_CTL1_DEVICE_EN		0x0080

#define MV88E6XXX_G1_CTL1_STATS_DONE_EN		0x0040

#define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN	0x0020

drivers/net/dsa/mv88e6xxx/global2.h

+8 −0
Original line number Diff line number Diff line
@@ -38,9 +38,15 @@ 
/* Offset 0x02: MGMT Enable Register 2x */

#define MV88E6XXX_G2_MGMT_EN_2X		0x02



/* Offset 0x02: MAC LINK change IRQ Register for MV88E6393X */

#define MV88E6393X_G2_MACLINK_INT_SRC		0x02



/* Offset 0x03: MGMT Enable Register 0x */

#define MV88E6XXX_G2_MGMT_EN_0X		0x03



/* Offset 0x03: MAC LINK change IRQ Mask Register for MV88E6393X */

#define MV88E6393X_G2_MACLINK_INT_MASK		0x03



/* Offset 0x04: Flow Control Delay Register */

#define MV88E6XXX_G2_FLOW_CTL	0x04
@@ -52,6 +58,8 @@ 
#define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI	0x0080

#define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU		0x0008



#define MV88E6393X_G2_EGRESS_MONITOR_DEST		0x05



/* Offset 0x06: Device Mapping Table Register */

#define MV88E6XXX_G2_DEVICE_MAPPING		0x06

#define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE	0x8000