Commit 4c5a331c authored by Hariprasad Kelam's avatar Hariprasad Kelam Committed by David S. Miller
Browse files

octeontx2-af: cn10kb: fix interrupt csr addresses 



The current design is that, for asynchronous events like link_up and
link_down firmware raises the interrupt to kernel. The previous patch
which added RPM_USX driver has a bug where it uses old csr addresses
for configuring interrupts. Which is resulting in losing interrupts
from source firmware.

This patch fixes the issue by correcting csr addresses.

Fixes: b9d0fedc ("octeontx2-af: cn10kb: Add RPM_USX MAC support")
Signed-off-by: default avatarHariprasad Kelam <hkelam@marvell.com>
Signed-off-by: default avatarSunil Goutham <sgoutham@marvell.com>
Reviewed-by: default avatarSimon Horman <simon.horman@corigine.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent c97d3fb9

drivers/net/ethernet/marvell/octeontx2/af/rpm.c

+1 −1
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ static struct mac_ops rpm2_mac_ops = { 
	.int_set_reg    =       RPM2_CMRX_SW_INT_ENA_W1S,

	.irq_offset     =       1,

	.int_ena_bit    =       BIT_ULL(0),

	.lmac_fwi	=	RPM_LMAC_FWI,

	.lmac_fwi	=	RPM2_LMAC_FWI,

	.non_contiguous_serdes_lane = true,

	.rx_stats_cnt   =       43,

	.tx_stats_cnt   =       34,

drivers/net/ethernet/marvell/octeontx2/af/rpm.h

+2 −1
Original line number Diff line number Diff line
@@ -94,7 +94,8 @@ 


/* CN10KB CSR Declaration */

#define  RPM2_CMRX_SW_INT				0x1b0

#define  RPM2_CMRX_SW_INT_ENA_W1S			0x1b8

#define  RPM2_CMRX_SW_INT_ENA_W1S			0x1c8

#define  RPM2_LMAC_FWI					0x12

#define  RPM2_CMR_CHAN_MSK_OR				0x3120

#define  RPM2_CMR_RX_OVR_BP_EN				BIT_ULL(2)

#define  RPM2_CMR_RX_OVR_BP_BP				BIT_ULL(1)