Loading arch/arm/mach-u300/core.c +159 −20 Original line number Diff line number Diff line Loading @@ -3,7 +3,7 @@ * arch/arm/mach-u300/core.c * * * Copyright (C) 2007-2010 ST-Ericsson AB * Copyright (C) 2007-2010 ST-Ericsson SA * License terms: GNU General Public License (GPL) version 2 * Core platform support, IRQ handling and device definitions. * Author: Linus Walleij <linus.walleij@stericsson.com> Loading @@ -16,7 +16,9 @@ #include <linux/device.h> #include <linux/mm.h> #include <linux/termios.h> #include <linux/dmaengine.h> #include <linux/amba/bus.h> #include <linux/amba/serial.h> #include <linux/platform_device.h> #include <linux/gpio.h> #include <linux/clk.h> Loading Loading @@ -96,10 +98,20 @@ void __init u300_map_io(void) * Declaration of devices found on the U300 board and * their respective memory locations. */ static struct amba_pl011_data uart0_plat_data = { #ifdef CONFIG_COH901318 .dma_filter = coh901318_filter_id, .dma_rx_param = (void *) U300_DMA_UART0_RX, .dma_tx_param = (void *) U300_DMA_UART0_TX, #endif }; static struct amba_device uart0_device = { .dev = { .coherent_dma_mask = ~0, .init_name = "uart0", /* Slow device at 0x3000 offset */ .platform_data = NULL, .platform_data = &uart0_plat_data, }, .res = { .start = U300_UART0_BASE, Loading @@ -111,10 +123,19 @@ static struct amba_device uart0_device = { /* The U335 have an additional UART1 on the APP CPU */ #ifdef CONFIG_MACH_U300_BS335 static struct amba_pl011_data uart1_plat_data = { #ifdef CONFIG_COH901318 .dma_filter = coh901318_filter_id, .dma_rx_param = (void *) U300_DMA_UART1_RX, .dma_tx_param = (void *) U300_DMA_UART1_TX, #endif }; static struct amba_device uart1_device = { .dev = { .coherent_dma_mask = ~0, .init_name = "uart1", /* Fast device at 0x7000 offset */ .platform_data = NULL, .platform_data = &uart1_plat_data, }, .res = { .start = U300_UART1_BASE, Loading Loading @@ -960,42 +981,37 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = { .priority_high = 0, .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220, }, /* * Don't set up device address, burst count or size of src * or dst bus for this peripheral - handled by PrimeCell * DMA extension. */ { .number = U300_DMA_MMCSD_RX_TX, .name = "MMCSD RX TX", .priority_high = 0, .dev_addr = U300_MMCSD_BASE + 0x080, .param.config = COH901318_CX_CFG_CH_DISABLE | COH901318_CX_CFG_LCR_DISABLE | COH901318_CX_CFG_TC_IRQ_ENABLE | COH901318_CX_CFG_BE_IRQ_ENABLE, .param.ctrl_lli_chained = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_ENABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_TC_IRQ_DISABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_ENABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_TC_IRQ_DISABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli_last = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_DISABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | Loading @@ -1014,15 +1030,76 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = { .name = "MSPRO RX", .priority_high = 0, }, /* * Don't set up device address, burst count or size of src * or dst bus for this peripheral - handled by PrimeCell * DMA extension. */ { .number = U300_DMA_UART0_TX, .name = "UART0 TX", .priority_high = 0, .param.config = COH901318_CX_CFG_CH_DISABLE | COH901318_CX_CFG_LCR_DISABLE | COH901318_CX_CFG_TC_IRQ_ENABLE | COH901318_CX_CFG_BE_IRQ_ENABLE, .param.ctrl_lli_chained = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_ENABLE | COH901318_CX_CTRL_TC_IRQ_DISABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_ENABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli_last = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_ENABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, }, { .number = U300_DMA_UART0_RX, .name = "UART0 RX", .priority_high = 0, .param.config = COH901318_CX_CFG_CH_DISABLE | COH901318_CX_CFG_LCR_DISABLE | COH901318_CX_CFG_TC_IRQ_ENABLE | COH901318_CX_CFG_BE_IRQ_ENABLE, .param.ctrl_lli_chained = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_ENABLE | COH901318_CX_CTRL_TC_IRQ_DISABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_ENABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli_last = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_ENABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, }, { .number = U300_DMA_APEX_TX, Loading Loading @@ -1080,7 +1157,7 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = { COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_ENABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_TC_IRQ_DISABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY | Loading Loading @@ -1252,15 +1329,77 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = { .name = "XGAM PDI", .priority_high = 0, }, /* * Don't set up device address, burst count or size of src * or dst bus for this peripheral - handled by PrimeCell * DMA extension. */ { .number = U300_DMA_SPI_TX, .name = "SPI TX", .priority_high = 0, .param.config = COH901318_CX_CFG_CH_DISABLE | COH901318_CX_CFG_LCR_DISABLE | COH901318_CX_CFG_TC_IRQ_ENABLE | COH901318_CX_CFG_BE_IRQ_ENABLE, .param.ctrl_lli_chained = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_DISABLE | COH901318_CX_CTRL_TC_IRQ_DISABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_DISABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli_last = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_DISABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, }, { .number = U300_DMA_SPI_RX, .name = "SPI RX", .priority_high = 0, .param.config = COH901318_CX_CFG_CH_DISABLE | COH901318_CX_CFG_LCR_DISABLE | COH901318_CX_CFG_TC_IRQ_ENABLE | COH901318_CX_CFG_BE_IRQ_ENABLE, .param.ctrl_lli_chained = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_DISABLE | COH901318_CX_CTRL_TC_IRQ_DISABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_DISABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli_last = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_DISABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, }, { .number = U300_DMA_GENERAL_PURPOSE_0, Loading Loading @@ -1617,7 +1756,7 @@ static void __init u300_init_check_chip(void) #endif #ifdef CONFIG_MACH_U300_BS335 if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) { printk(KERN_ERR "Platform configured for BS365 " \ printk(KERN_ERR "Platform configured for BS335 " \ " with DB3350 but %s detected, expect problems!", chipname); } Loading Loading @@ -1692,12 +1831,12 @@ void __init u300_init_devices(void) /* Register subdevices on the I2C buses */ u300_i2c_register_board_devices(); /* Register subdevices on the SPI bus */ u300_spi_register_board_devices(); /* Register the platform devices */ platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); /* Register subdevices on the SPI bus */ u300_spi_register_board_devices(); #ifndef CONFIG_MACH_U300_SEMI_IS_SHARED /* * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when Loading arch/arm/mach-u300/include/mach/coh901318.h +7 −0 Original line number Diff line number Diff line Loading @@ -102,6 +102,7 @@ struct coh901318_platform { const int max_channels; }; #ifdef CONFIG_COH901318 /** * coh901318_filter_id() - DMA channel filter function * @chan: dma channel handle Loading @@ -110,6 +111,12 @@ struct coh901318_platform { * In dma_request_channel() it specifies what channel id to be requested */ bool coh901318_filter_id(struct dma_chan *chan, void *chan_id); #else static inline bool coh901318_filter_id(struct dma_chan *chan, void *chan_id) { return false; } #endif /* * DMA Controller - this access the static mappings of the coh901318 dma. Loading arch/arm/mach-u300/mmc.c +23 −137 Original line number Diff line number Diff line Loading @@ -3,159 +3,52 @@ * arch/arm/mach-u300/mmc.c * * * Copyright (C) 2009 ST-Ericsson AB * Copyright (C) 2009 ST-Ericsson SA * License terms: GNU General Public License (GPL) version 2 * * Author: Linus Walleij <linus.walleij@stericsson.com> * Author: Johan Lundin <johan.lundin@stericsson.com> * Author: Johan Lundin * Author: Jonas Aaberg <jonas.aberg@stericsson.com> */ #include <linux/device.h> #include <linux/amba/bus.h> #include <linux/mmc/host.h> #include <linux/input.h> #include <linux/workqueue.h> #include <linux/delay.h> #include <linux/regulator/consumer.h> #include <linux/regulator/machine.h> #include <linux/gpio.h> #include <linux/dmaengine.h> #include <linux/amba/mmci.h> #include <linux/slab.h> #include <mach/coh901318.h> #include <mach/dma_channels.h> #include "mmc.h" #include "padmux.h" struct mmci_card_event { struct input_dev *mmc_input; int mmc_inserted; struct work_struct workq; struct mmci_platform_data mmc0_plat_data; static struct mmci_platform_data mmc0_plat_data = { /* * Do not set ocr_mask or voltage translation function, * we have a regulator we can control instead. */ /* Nominally 2.85V on our platform */ .f_max = 24000000, .gpio_wp = -1, .gpio_cd = U300_GPIO_PIN_MMC_CD, .cd_invert = true, .capabilities = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, #ifdef CONFIG_COH901318 .dma_filter = coh901318_filter_id, .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX, /* Don't specify a TX channel, this RX channel is bidirectional */ #endif }; static unsigned int mmc_status(struct device *dev) { struct mmci_card_event *mmci_card = container_of( dev->platform_data, struct mmci_card_event, mmc0_plat_data); return mmci_card->mmc_inserted; } static int mmci_callback(void *data) { struct mmci_card_event *mmci_card = data; disable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD); schedule_work(&mmci_card->workq); return 0; } static ssize_t gpio_show(struct device *dev, struct device_attribute *attr, char *buf) { struct mmci_card_event *mmci_card = container_of( dev->platform_data, struct mmci_card_event, mmc0_plat_data); return sprintf(buf, "%d\n", !mmci_card->mmc_inserted); } static DEVICE_ATTR(mmc_inserted, S_IRUGO, gpio_show, NULL); static void _mmci_callback(struct work_struct *ws) { struct mmci_card_event *mmci_card = container_of( ws, struct mmci_card_event, workq); mdelay(20); mmci_card->mmc_inserted = !gpio_get_value(U300_GPIO_PIN_MMC_CD); input_report_switch(mmci_card->mmc_input, KEY_INSERT, mmci_card->mmc_inserted); input_sync(mmci_card->mmc_input); pr_debug("MMC/SD card was %s\n", mmci_card->mmc_inserted ? "inserted" : "removed"); enable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD, mmci_card->mmc_inserted); } int __devinit mmc_init(struct amba_device *adev) { struct mmci_card_event *mmci_card; struct device *mmcsd_device = &adev->dev; struct pmx *pmx; int ret = 0; mmci_card = kzalloc(sizeof(struct mmci_card_event), GFP_KERNEL); if (!mmci_card) return -ENOMEM; /* * Do not set ocr_mask or voltage translation function, * we have a regulator we can control instead. */ /* Nominally 2.85V on our platform */ mmci_card->mmc0_plat_data.f_max = 24000000; mmci_card->mmc0_plat_data.status = mmc_status; mmci_card->mmc0_plat_data.gpio_wp = -1; mmci_card->mmc0_plat_data.gpio_cd = -1; mmci_card->mmc0_plat_data.capabilities = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; mmcsd_device->platform_data = (void *) &mmci_card->mmc0_plat_data; INIT_WORK(&mmci_card->workq, _mmci_callback); ret = gpio_request(U300_GPIO_PIN_MMC_CD, "MMC card detection"); if (ret) { printk(KERN_CRIT "Could not allocate MMC card detection " \ "GPIO pin\n"); goto out; } ret = gpio_direction_input(U300_GPIO_PIN_MMC_CD); if (ret) { printk(KERN_CRIT "Invalid GPIO pin requested\n"); goto out; } ret = sysfs_create_file(&mmcsd_device->kobj, &dev_attr_mmc_inserted.attr); if (ret) goto out; mmci_card->mmc_input = input_allocate_device(); if (!mmci_card->mmc_input) { printk(KERN_CRIT "Could not allocate MMC input device\n"); return -ENOMEM; } mmci_card->mmc_input->name = "MMC insert notification"; mmci_card->mmc_input->id.bustype = BUS_HOST; mmci_card->mmc_input->id.vendor = 0; mmci_card->mmc_input->id.product = 0; mmci_card->mmc_input->id.version = 0x0100; mmci_card->mmc_input->dev.parent = mmcsd_device; input_set_capability(mmci_card->mmc_input, EV_SW, KEY_INSERT); /* * Since this must always be compiled into the kernel, this input * is never unregistered or free:ed. */ ret = input_register_device(mmci_card->mmc_input); if (ret) { input_free_device(mmci_card->mmc_input); goto out; } input_set_drvdata(mmci_card->mmc_input, mmci_card); mmcsd_device->platform_data = &mmc0_plat_data; /* * Setup padmuxing for MMC. Since this must always be Loading @@ -171,12 +64,5 @@ int __devinit mmc_init(struct amba_device *adev) pr_warning("Could not activate padmuxing\n"); } ret = gpio_register_callback(U300_GPIO_PIN_MMC_CD, mmci_callback, mmci_card); schedule_work(&mmci_card->workq); printk(KERN_INFO "Registered MMC insert/remove notification\n"); out: return ret; } arch/arm/mach-u300/spi.c +14 −7 Original line number Diff line number Diff line Loading @@ -11,6 +11,9 @@ #include <linux/spi/spi.h> #include <linux/amba/pl022.h> #include <linux/err.h> #include <mach/coh901318.h> #include <mach/dma_channels.h> #include "padmux.h" /* Loading @@ -30,11 +33,8 @@ static void select_dummy_chip(u32 chipselect) } struct pl022_config_chip dummy_chip_info = { /* * available POLLING_TRANSFER and INTERRUPT_TRANSFER, * DMA_TRANSFER does not work */ .com_mode = INTERRUPT_TRANSFER, /* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */ .com_mode = DMA_TRANSFER, .iface = SSP_INTERFACE_MOTOROLA_SPI, /* We can only act as master but SSP_SLAVE is possible in theory */ .hierarchy = SSP_MASTER, Loading Loading @@ -75,8 +75,6 @@ static struct spi_board_info u300_spi_devices[] = { static struct pl022_ssp_controller ssp_platform_data = { /* If you have several SPI buses this varies, we have only bus 0 */ .bus_id = 0, /* Set this to 1 when we think we got DMA working */ .enable_dma = 0, /* * On the APP CPU GPIO 4, 5 and 6 are connected as generic * chip selects for SPI. (Same on U330, U335 and U365.) Loading @@ -84,6 +82,14 @@ static struct pl022_ssp_controller ssp_platform_data = { * and do padmuxing accordingly too. */ .num_chipselect = 3, #ifdef CONFIG_COH901318 .enable_dma = 1, .dma_filter = coh901318_filter_id, .dma_rx_param = (void *) U300_DMA_SPI_RX, .dma_tx_param = (void *) U300_DMA_SPI_TX, #else .enable_dma = 0, #endif }; Loading @@ -109,6 +115,7 @@ void __init u300_spi_init(struct amba_device *adev) } } void __init u300_spi_register_board_devices(void) { /* Register any SPI devices */ Loading arch/arm/mach-ux500/Makefile +5 −3 Original line number Diff line number Diff line Loading @@ -3,16 +3,18 @@ # obj-y := clock.o cpu.o devices.o devices-common.o \ id.o id.o usb.o obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o prcmu.o obj-$(CONFIG_MACH_U8500) += board-mop500.o board-mop500-sdi.o \ board-mop500-keypads.o board-mop500-regulators.o \ board-mop500-uib.o board-mop500-stuib.o \ board-mop500-u8500uib.o \ board-mop500-pins.o obj-$(CONFIG_MACH_U5500) += board-u5500.o board-u5500-sdi.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o obj-$(CONFIG_REGULATOR_AB8500) += board-mop500-regulators.o obj-$(CONFIG_U5500_MODEM_IRQ) += modem-irq-db5500.o obj-$(CONFIG_U5500_MBOX) += mbox-db5500.o obj-$(CONFIG_CPU_FREQ) += cpufreq.o Loading
arch/arm/mach-u300/core.c +159 −20 Original line number Diff line number Diff line Loading @@ -3,7 +3,7 @@ * arch/arm/mach-u300/core.c * * * Copyright (C) 2007-2010 ST-Ericsson AB * Copyright (C) 2007-2010 ST-Ericsson SA * License terms: GNU General Public License (GPL) version 2 * Core platform support, IRQ handling and device definitions. * Author: Linus Walleij <linus.walleij@stericsson.com> Loading @@ -16,7 +16,9 @@ #include <linux/device.h> #include <linux/mm.h> #include <linux/termios.h> #include <linux/dmaengine.h> #include <linux/amba/bus.h> #include <linux/amba/serial.h> #include <linux/platform_device.h> #include <linux/gpio.h> #include <linux/clk.h> Loading Loading @@ -96,10 +98,20 @@ void __init u300_map_io(void) * Declaration of devices found on the U300 board and * their respective memory locations. */ static struct amba_pl011_data uart0_plat_data = { #ifdef CONFIG_COH901318 .dma_filter = coh901318_filter_id, .dma_rx_param = (void *) U300_DMA_UART0_RX, .dma_tx_param = (void *) U300_DMA_UART0_TX, #endif }; static struct amba_device uart0_device = { .dev = { .coherent_dma_mask = ~0, .init_name = "uart0", /* Slow device at 0x3000 offset */ .platform_data = NULL, .platform_data = &uart0_plat_data, }, .res = { .start = U300_UART0_BASE, Loading @@ -111,10 +123,19 @@ static struct amba_device uart0_device = { /* The U335 have an additional UART1 on the APP CPU */ #ifdef CONFIG_MACH_U300_BS335 static struct amba_pl011_data uart1_plat_data = { #ifdef CONFIG_COH901318 .dma_filter = coh901318_filter_id, .dma_rx_param = (void *) U300_DMA_UART1_RX, .dma_tx_param = (void *) U300_DMA_UART1_TX, #endif }; static struct amba_device uart1_device = { .dev = { .coherent_dma_mask = ~0, .init_name = "uart1", /* Fast device at 0x7000 offset */ .platform_data = NULL, .platform_data = &uart1_plat_data, }, .res = { .start = U300_UART1_BASE, Loading Loading @@ -960,42 +981,37 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = { .priority_high = 0, .dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220, }, /* * Don't set up device address, burst count or size of src * or dst bus for this peripheral - handled by PrimeCell * DMA extension. */ { .number = U300_DMA_MMCSD_RX_TX, .name = "MMCSD RX TX", .priority_high = 0, .dev_addr = U300_MMCSD_BASE + 0x080, .param.config = COH901318_CX_CFG_CH_DISABLE | COH901318_CX_CFG_LCR_DISABLE | COH901318_CX_CFG_TC_IRQ_ENABLE | COH901318_CX_CFG_BE_IRQ_ENABLE, .param.ctrl_lli_chained = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_ENABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_TC_IRQ_DISABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_ENABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_TC_IRQ_DISABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli_last = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_BURST_COUNT_32_BYTES | COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_DISABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | Loading @@ -1014,15 +1030,76 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = { .name = "MSPRO RX", .priority_high = 0, }, /* * Don't set up device address, burst count or size of src * or dst bus for this peripheral - handled by PrimeCell * DMA extension. */ { .number = U300_DMA_UART0_TX, .name = "UART0 TX", .priority_high = 0, .param.config = COH901318_CX_CFG_CH_DISABLE | COH901318_CX_CFG_LCR_DISABLE | COH901318_CX_CFG_TC_IRQ_ENABLE | COH901318_CX_CFG_BE_IRQ_ENABLE, .param.ctrl_lli_chained = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_ENABLE | COH901318_CX_CTRL_TC_IRQ_DISABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_ENABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli_last = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_ENABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, }, { .number = U300_DMA_UART0_RX, .name = "UART0 RX", .priority_high = 0, .param.config = COH901318_CX_CFG_CH_DISABLE | COH901318_CX_CFG_LCR_DISABLE | COH901318_CX_CFG_TC_IRQ_ENABLE | COH901318_CX_CFG_BE_IRQ_ENABLE, .param.ctrl_lli_chained = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_ENABLE | COH901318_CX_CTRL_TC_IRQ_DISABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_ENABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli_last = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_ENABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, }, { .number = U300_DMA_APEX_TX, Loading Loading @@ -1080,7 +1157,7 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = { COH901318_CX_CTRL_DST_ADDR_INC_DISABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_ENABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_TC_IRQ_DISABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY | Loading Loading @@ -1252,15 +1329,77 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = { .name = "XGAM PDI", .priority_high = 0, }, /* * Don't set up device address, burst count or size of src * or dst bus for this peripheral - handled by PrimeCell * DMA extension. */ { .number = U300_DMA_SPI_TX, .name = "SPI TX", .priority_high = 0, .param.config = COH901318_CX_CFG_CH_DISABLE | COH901318_CX_CFG_LCR_DISABLE | COH901318_CX_CFG_TC_IRQ_ENABLE | COH901318_CX_CFG_BE_IRQ_ENABLE, .param.ctrl_lli_chained = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_DISABLE | COH901318_CX_CTRL_TC_IRQ_DISABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_DISABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli_last = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_DISABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, }, { .number = U300_DMA_SPI_RX, .name = "SPI RX", .priority_high = 0, .param.config = COH901318_CX_CFG_CH_DISABLE | COH901318_CX_CFG_LCR_DISABLE | COH901318_CX_CFG_TC_IRQ_ENABLE | COH901318_CX_CFG_BE_IRQ_ENABLE, .param.ctrl_lli_chained = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_DISABLE | COH901318_CX_CTRL_TC_IRQ_DISABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_DISABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, .param.ctrl_lli_last = 0 | COH901318_CX_CTRL_TC_ENABLE | COH901318_CX_CTRL_MASTER_MODE_M1RW | COH901318_CX_CTRL_TCP_DISABLE | COH901318_CX_CTRL_TC_IRQ_ENABLE | COH901318_CX_CTRL_HSP_ENABLE | COH901318_CX_CTRL_HSS_DISABLE | COH901318_CX_CTRL_DDMA_LEGACY, }, { .number = U300_DMA_GENERAL_PURPOSE_0, Loading Loading @@ -1617,7 +1756,7 @@ static void __init u300_init_check_chip(void) #endif #ifdef CONFIG_MACH_U300_BS335 if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) { printk(KERN_ERR "Platform configured for BS365 " \ printk(KERN_ERR "Platform configured for BS335 " \ " with DB3350 but %s detected, expect problems!", chipname); } Loading Loading @@ -1692,12 +1831,12 @@ void __init u300_init_devices(void) /* Register subdevices on the I2C buses */ u300_i2c_register_board_devices(); /* Register subdevices on the SPI bus */ u300_spi_register_board_devices(); /* Register the platform devices */ platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs)); /* Register subdevices on the SPI bus */ u300_spi_register_board_devices(); #ifndef CONFIG_MACH_U300_SEMI_IS_SHARED /* * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when Loading
arch/arm/mach-u300/include/mach/coh901318.h +7 −0 Original line number Diff line number Diff line Loading @@ -102,6 +102,7 @@ struct coh901318_platform { const int max_channels; }; #ifdef CONFIG_COH901318 /** * coh901318_filter_id() - DMA channel filter function * @chan: dma channel handle Loading @@ -110,6 +111,12 @@ struct coh901318_platform { * In dma_request_channel() it specifies what channel id to be requested */ bool coh901318_filter_id(struct dma_chan *chan, void *chan_id); #else static inline bool coh901318_filter_id(struct dma_chan *chan, void *chan_id) { return false; } #endif /* * DMA Controller - this access the static mappings of the coh901318 dma. Loading
arch/arm/mach-u300/mmc.c +23 −137 Original line number Diff line number Diff line Loading @@ -3,159 +3,52 @@ * arch/arm/mach-u300/mmc.c * * * Copyright (C) 2009 ST-Ericsson AB * Copyright (C) 2009 ST-Ericsson SA * License terms: GNU General Public License (GPL) version 2 * * Author: Linus Walleij <linus.walleij@stericsson.com> * Author: Johan Lundin <johan.lundin@stericsson.com> * Author: Johan Lundin * Author: Jonas Aaberg <jonas.aberg@stericsson.com> */ #include <linux/device.h> #include <linux/amba/bus.h> #include <linux/mmc/host.h> #include <linux/input.h> #include <linux/workqueue.h> #include <linux/delay.h> #include <linux/regulator/consumer.h> #include <linux/regulator/machine.h> #include <linux/gpio.h> #include <linux/dmaengine.h> #include <linux/amba/mmci.h> #include <linux/slab.h> #include <mach/coh901318.h> #include <mach/dma_channels.h> #include "mmc.h" #include "padmux.h" struct mmci_card_event { struct input_dev *mmc_input; int mmc_inserted; struct work_struct workq; struct mmci_platform_data mmc0_plat_data; static struct mmci_platform_data mmc0_plat_data = { /* * Do not set ocr_mask or voltage translation function, * we have a regulator we can control instead. */ /* Nominally 2.85V on our platform */ .f_max = 24000000, .gpio_wp = -1, .gpio_cd = U300_GPIO_PIN_MMC_CD, .cd_invert = true, .capabilities = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, #ifdef CONFIG_COH901318 .dma_filter = coh901318_filter_id, .dma_rx_param = (void *) U300_DMA_MMCSD_RX_TX, /* Don't specify a TX channel, this RX channel is bidirectional */ #endif }; static unsigned int mmc_status(struct device *dev) { struct mmci_card_event *mmci_card = container_of( dev->platform_data, struct mmci_card_event, mmc0_plat_data); return mmci_card->mmc_inserted; } static int mmci_callback(void *data) { struct mmci_card_event *mmci_card = data; disable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD); schedule_work(&mmci_card->workq); return 0; } static ssize_t gpio_show(struct device *dev, struct device_attribute *attr, char *buf) { struct mmci_card_event *mmci_card = container_of( dev->platform_data, struct mmci_card_event, mmc0_plat_data); return sprintf(buf, "%d\n", !mmci_card->mmc_inserted); } static DEVICE_ATTR(mmc_inserted, S_IRUGO, gpio_show, NULL); static void _mmci_callback(struct work_struct *ws) { struct mmci_card_event *mmci_card = container_of( ws, struct mmci_card_event, workq); mdelay(20); mmci_card->mmc_inserted = !gpio_get_value(U300_GPIO_PIN_MMC_CD); input_report_switch(mmci_card->mmc_input, KEY_INSERT, mmci_card->mmc_inserted); input_sync(mmci_card->mmc_input); pr_debug("MMC/SD card was %s\n", mmci_card->mmc_inserted ? "inserted" : "removed"); enable_irq_on_gpio_pin(U300_GPIO_PIN_MMC_CD, mmci_card->mmc_inserted); } int __devinit mmc_init(struct amba_device *adev) { struct mmci_card_event *mmci_card; struct device *mmcsd_device = &adev->dev; struct pmx *pmx; int ret = 0; mmci_card = kzalloc(sizeof(struct mmci_card_event), GFP_KERNEL); if (!mmci_card) return -ENOMEM; /* * Do not set ocr_mask or voltage translation function, * we have a regulator we can control instead. */ /* Nominally 2.85V on our platform */ mmci_card->mmc0_plat_data.f_max = 24000000; mmci_card->mmc0_plat_data.status = mmc_status; mmci_card->mmc0_plat_data.gpio_wp = -1; mmci_card->mmc0_plat_data.gpio_cd = -1; mmci_card->mmc0_plat_data.capabilities = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA; mmcsd_device->platform_data = (void *) &mmci_card->mmc0_plat_data; INIT_WORK(&mmci_card->workq, _mmci_callback); ret = gpio_request(U300_GPIO_PIN_MMC_CD, "MMC card detection"); if (ret) { printk(KERN_CRIT "Could not allocate MMC card detection " \ "GPIO pin\n"); goto out; } ret = gpio_direction_input(U300_GPIO_PIN_MMC_CD); if (ret) { printk(KERN_CRIT "Invalid GPIO pin requested\n"); goto out; } ret = sysfs_create_file(&mmcsd_device->kobj, &dev_attr_mmc_inserted.attr); if (ret) goto out; mmci_card->mmc_input = input_allocate_device(); if (!mmci_card->mmc_input) { printk(KERN_CRIT "Could not allocate MMC input device\n"); return -ENOMEM; } mmci_card->mmc_input->name = "MMC insert notification"; mmci_card->mmc_input->id.bustype = BUS_HOST; mmci_card->mmc_input->id.vendor = 0; mmci_card->mmc_input->id.product = 0; mmci_card->mmc_input->id.version = 0x0100; mmci_card->mmc_input->dev.parent = mmcsd_device; input_set_capability(mmci_card->mmc_input, EV_SW, KEY_INSERT); /* * Since this must always be compiled into the kernel, this input * is never unregistered or free:ed. */ ret = input_register_device(mmci_card->mmc_input); if (ret) { input_free_device(mmci_card->mmc_input); goto out; } input_set_drvdata(mmci_card->mmc_input, mmci_card); mmcsd_device->platform_data = &mmc0_plat_data; /* * Setup padmuxing for MMC. Since this must always be Loading @@ -171,12 +64,5 @@ int __devinit mmc_init(struct amba_device *adev) pr_warning("Could not activate padmuxing\n"); } ret = gpio_register_callback(U300_GPIO_PIN_MMC_CD, mmci_callback, mmci_card); schedule_work(&mmci_card->workq); printk(KERN_INFO "Registered MMC insert/remove notification\n"); out: return ret; }
arch/arm/mach-u300/spi.c +14 −7 Original line number Diff line number Diff line Loading @@ -11,6 +11,9 @@ #include <linux/spi/spi.h> #include <linux/amba/pl022.h> #include <linux/err.h> #include <mach/coh901318.h> #include <mach/dma_channels.h> #include "padmux.h" /* Loading @@ -30,11 +33,8 @@ static void select_dummy_chip(u32 chipselect) } struct pl022_config_chip dummy_chip_info = { /* * available POLLING_TRANSFER and INTERRUPT_TRANSFER, * DMA_TRANSFER does not work */ .com_mode = INTERRUPT_TRANSFER, /* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */ .com_mode = DMA_TRANSFER, .iface = SSP_INTERFACE_MOTOROLA_SPI, /* We can only act as master but SSP_SLAVE is possible in theory */ .hierarchy = SSP_MASTER, Loading Loading @@ -75,8 +75,6 @@ static struct spi_board_info u300_spi_devices[] = { static struct pl022_ssp_controller ssp_platform_data = { /* If you have several SPI buses this varies, we have only bus 0 */ .bus_id = 0, /* Set this to 1 when we think we got DMA working */ .enable_dma = 0, /* * On the APP CPU GPIO 4, 5 and 6 are connected as generic * chip selects for SPI. (Same on U330, U335 and U365.) Loading @@ -84,6 +82,14 @@ static struct pl022_ssp_controller ssp_platform_data = { * and do padmuxing accordingly too. */ .num_chipselect = 3, #ifdef CONFIG_COH901318 .enable_dma = 1, .dma_filter = coh901318_filter_id, .dma_rx_param = (void *) U300_DMA_SPI_RX, .dma_tx_param = (void *) U300_DMA_SPI_TX, #else .enable_dma = 0, #endif }; Loading @@ -109,6 +115,7 @@ void __init u300_spi_init(struct amba_device *adev) } } void __init u300_spi_register_board_devices(void) { /* Register any SPI devices */ Loading
arch/arm/mach-ux500/Makefile +5 −3 Original line number Diff line number Diff line Loading @@ -3,16 +3,18 @@ # obj-y := clock.o cpu.o devices.o devices-common.o \ id.o id.o usb.o obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o prcmu.o obj-$(CONFIG_MACH_U8500) += board-mop500.o board-mop500-sdi.o \ board-mop500-keypads.o board-mop500-regulators.o \ board-mop500-uib.o board-mop500-stuib.o \ board-mop500-u8500uib.o \ board-mop500-pins.o obj-$(CONFIG_MACH_U5500) += board-u5500.o board-u5500-sdi.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o obj-$(CONFIG_REGULATOR_AB8500) += board-mop500-regulators.o obj-$(CONFIG_U5500_MODEM_IRQ) += modem-irq-db5500.o obj-$(CONFIG_U5500_MBOX) += mbox-db5500.o obj-$(CONFIG_CPU_FREQ) += cpufreq.o