Commit 4c12f41a authored by Zhengjun Xing's avatar Zhengjun Xing Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Update events and metrics for alderlake 

Update JSON events and metrics for alderlake to perf.

Based on ADL JSON event list v1.16:

https://github.com/intel/perfmon/tree/main/ADL/events

Generate the event list and metrics with the converter scripts:

https://github.com/intel/perfmon/pull/32



Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarXing Zhengjun <zhengjun.xing@linux.intel.com>
Acked-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20221124031441.110134-4-zhengjun.xing@linux.intel.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 2bb3fbad

tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json

+48 −25
Original line number Diff line number Diff line
@@ -1287,14 +1287,14 @@ 
    },

    {

        "BriefDescription": "Average CPU Utilization",

        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",

        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",

        "MetricGroup": "HPC;Summary",

        "MetricName": "CPU_Utilization",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",

        "MetricExpr": "Turbo_Utilization * msr@tsc@ / 1000000000 / duration_time",

        "MetricExpr": "Turbo_Utilization * TSC / 1000000000 / duration_time",

        "MetricGroup": "Power;Summary",

        "MetricName": "Average_Frequency",

        "Unit": "cpu_core"
@@ -1337,18 +1337,25 @@ 
    },

    {

        "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",

        "MetricExpr": "64 * (arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@) / 1000000 / duration_time / 1000",

        "MetricExpr": "64 * (UNC_ARB_TRK_REQUESTS.ALL + UNC_ARB_COH_TRK_REQUESTS.ALL) / 1000000 / duration_time / 1000",

        "MetricGroup": "HPC;Mem;MemoryBW;SoC",

        "MetricName": "DRAM_BW_Use",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Average number of parallel requests to external memory. Accounts for all requests",

        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / arb@event\\=0x81\\,umask\\=0x1@",

        "MetricExpr": "UNC_ARB_TRK_OCCUPANCY.ALL / UNC_ARB_TRK_REQUESTS.ALL",

        "MetricGroup": "Mem;SoC",

        "MetricName": "MEM_Parallel_Requests",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Socket actual clocks when any core is active on that socket",

        "MetricExpr": "UNC_CLOCK.SOCKET",

        "MetricGroup": "SoC",

        "MetricName": "Socket_CLKS",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",

        "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
@@ -1356,6 +1363,12 @@ 
        "MetricName": "IpFarBranch",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Uncore frequency per die [GHZ]",

        "MetricExpr": "Socket_CLKS / #num_dies / duration_time / 1000000000",

        "MetricGroup": "SoC",

        "MetricName": "UNCORE_FREQ"

    },

    {

        "BriefDescription": "Counts the number of issue slots  that were not consumed by the backend due to frontend stalls.",

        "MetricExpr": "TOPDOWN_FE_BOUND.ALL / SLOTS",
@@ -1902,7 +1915,7 @@ 
    },

    {

        "BriefDescription": "Average CPU Utilization",

        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",

        "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC",

        "MetricName": "CPU_Utilization",

        "Unit": "cpu_atom"

    },
@@ -1950,62 +1963,72 @@ 
    },

    {

        "BriefDescription": "C1 residency percent per core",

        "MetricExpr": "(cstate_core@c1\\-residency@ / msr@tsc@) * 100",

        "MetricExpr": "cstate_core@c1\\-residency@ / TSC",

        "MetricGroup": "Power",

        "MetricName": "C1_Core_Residency"

        "MetricName": "C1_Core_Residency",

        "ScaleUnit": "100%"

    },

    {

        "BriefDescription": "C6 residency percent per core",

        "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100",

        "MetricExpr": "cstate_core@c6\\-residency@ / TSC",

        "MetricGroup": "Power",

        "MetricName": "C6_Core_Residency"

        "MetricName": "C6_Core_Residency",

        "ScaleUnit": "100%"

    },

    {

        "BriefDescription": "C7 residency percent per core",

        "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100",

        "MetricExpr": "cstate_core@c7\\-residency@ / TSC",

        "MetricGroup": "Power",

        "MetricName": "C7_Core_Residency"

        "MetricName": "C7_Core_Residency",

        "ScaleUnit": "100%"

    },

    {

        "BriefDescription": "C2 residency percent per package",

        "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100",

        "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC",

        "MetricGroup": "Power",

        "MetricName": "C2_Pkg_Residency"

        "MetricName": "C2_Pkg_Residency",

        "ScaleUnit": "100%"

    },

    {

        "BriefDescription": "C3 residency percent per package",

        "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100",

        "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC",

        "MetricGroup": "Power",

        "MetricName": "C3_Pkg_Residency"

        "MetricName": "C3_Pkg_Residency",

        "ScaleUnit": "100%"

    },

    {

        "BriefDescription": "C6 residency percent per package",

        "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100",

        "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC",

        "MetricGroup": "Power",

        "MetricName": "C6_Pkg_Residency"

        "MetricName": "C6_Pkg_Residency",

        "ScaleUnit": "100%"

    },

    {

        "BriefDescription": "C7 residency percent per package",

        "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100",

        "MetricExpr": "cstate_pkg@c7\\-residency@ / TSC",

        "MetricGroup": "Power",

        "MetricName": "C7_Pkg_Residency"

        "MetricName": "C7_Pkg_Residency",

        "ScaleUnit": "100%"

    },

    {

        "BriefDescription": "C8 residency percent per package",

        "MetricExpr": "(cstate_pkg@c8\\-residency@ / msr@tsc@) * 100",

        "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC",

        "MetricGroup": "Power",

        "MetricName": "C8_Pkg_Residency"

        "MetricName": "C8_Pkg_Residency",

        "ScaleUnit": "100%"

    },

    {

        "BriefDescription": "C9 residency percent per package",

        "MetricExpr": "(cstate_pkg@c9\\-residency@ / msr@tsc@) * 100",

        "MetricExpr": "cstate_pkg@c9\\-residency@ / TSC",

        "MetricGroup": "Power",

        "MetricName": "C9_Pkg_Residency"

        "MetricName": "C9_Pkg_Residency",

        "ScaleUnit": "100%"

    },

    {

        "BriefDescription": "C10 residency percent per package",

        "MetricExpr": "(cstate_pkg@c10\\-residency@ / msr@tsc@) * 100",

        "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC",

        "MetricGroup": "Power",

        "MetricName": "C10_Pkg_Residency"

        "MetricName": "C10_Pkg_Residency",

        "ScaleUnit": "100%"

    }

]

tools/perf/pmu-events/arch/x86/alderlake/cache.json

+547 −844

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tools/perf/pmu-events/arch/x86/alderlake/floating-point.json

+25 −66
Original line number Diff line number Diff line 
[

    {

        "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5",

        "EventCode": "0xc3",

        "EventName": "MACHINE_CLEARS.FP_ASSIST",

        "PEBScounters": "0,1,2,3,4,5",

        "SampleAfterValue": "20003",

        "Speculative": "1",

        "UMask": "0x4",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5",

        "EventCode": "0xc2",

        "EventName": "UOPS_RETIRED.FPDIV",

        "PEBS": "1",

        "PEBScounters": "0,1,2,3,4,5",

        "SampleAfterValue": "2000003",

        "UMask": "0x8",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "ARITH.FPDIV_ACTIVE",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "CounterMask": "1",

        "EventCode": "0xb0",

        "EventName": "ARITH.FPDIV_ACTIVE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts all microcode FP assists.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc1",

        "EventName": "ASSISTS.FP",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "PublicDescription": "Counts all microcode Floating Point assists.",

        "SampleAfterValue": "100003",

        "Speculative": "1",

        "UMask": "0x2",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "ASSISTS.SSE_AVX_MIX",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc1",

        "EventName": "ASSISTS.SSE_AVX_MIX",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "1000003",

        "Speculative": "1",

        "UMask": "0x10",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xb3",

        "EventName": "FP_ARITH_DISPATCHED.PORT_0",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "2000003",

        "Speculative": "1",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xb3",

        "EventName": "FP_ARITH_DISPATCHED.PORT_1",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "2000003",

        "Speculative": "1",

        "UMask": "0x2",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xb3",

        "EventName": "FP_ARITH_DISPATCHED.PORT_5",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "SampleAfterValue": "2000003",

        "Speculative": "1",

        "UMask": "0x4",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "PublicDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 2 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "100003",

        "UMask": "0x4",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "PublicDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "100003",

        "UMask": "0x8",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "PublicDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 4 computation operations, one for each element.  Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "100003",

        "UMask": "0x10",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "PublicDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 8 computation operations, one for each element.  Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB.  DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "100003",

        "UMask": "0x20",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "PublicDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "100003",

        "UMask": "0x1",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",

        "CollectPEBSRecord": "2",

        "Counter": "0,1,2,3,4,5,6,7",

        "EventCode": "0xc7",

        "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",

        "PEBScounters": "0,1,2,3,4,5,6,7",

        "PublicDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below.  Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.  FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR register need to be set when using these events.",

        "SampleAfterValue": "100003",

        "UMask": "0x2",

        "Unit": "cpu_core"

    },

    {

        "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",

        "EventCode": "0xc3",

        "EventName": "MACHINE_CLEARS.FP_ASSIST",

        "PublicDescription": "Counts the number of floating point operations retired that required microcode assist, which is not a reflection of the number of FP operations, instructions or uops.",

        "SampleAfterValue": "20003",

        "UMask": "0x4",

        "Unit": "cpu_atom"

    },

    {

        "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",

        "EventCode": "0xc2",

        "EventName": "UOPS_RETIRED.FPDIV",

        "PEBS": "1",

        "SampleAfterValue": "2000003",

        "UMask": "0x8",

        "Unit": "cpu_atom"

    }

]

tools/perf/pmu-events/arch/x86/alderlake/frontend.json

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tools/perf/pmu-events/arch/x86/alderlake/memory.json

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