Commit 4bce2442 authored by Marco Felsch's avatar Marco Felsch Committed by Lucas Stach
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drm/etnaviv: disable tx clock gating for GC7000 rev6203 



The i.MX8MN SoC errata sheet mentions ERR050226: "GPU: Texture L2 Cache
idle signal may incorrectly clock gate the texture engine in GPU".

The workaround is to disable the corresponding clock gatings.

While on it move the clock gating check for rev6202 into the same check
to bundle them.

Signed-off-by: default avatarMarco Felsch <m.felsch@pengutronix.de>
Reviewed-by: default avatarChristian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
parent d37c120b

drivers/gpu/drm/etnaviv/etnaviv_gpu.c

+5 −4
Original line number Diff line number Diff line
@@ -623,14 +623,15 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) 


	/* Disable TX clock gating on affected core revisions. */

	if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||

	    etnaviv_is_model_rev(gpu, GC2000, 0x5108))

	    etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||

	    etnaviv_is_model_rev(gpu, GC2000, 0x6202) ||

	    etnaviv_is_model_rev(gpu, GC2000, 0x6203))

		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;



	/* Disable SE, RA and TX clock gating on affected core revisions. */

	/* Disable SE and RA clock gating on affected core revisions. */

	if (etnaviv_is_model_rev(gpu, GC7000, 0x6202))

		pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE |

		       VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA |

		       VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;

		       VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA;



	pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;

	pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;