Commit 4b95d371 authored by Jonathan Marek's avatar Jonathan Marek Committed by Rob Clark
Browse files

drm/msm: fix LLC not being enabled for mmu500 targets 



mmu500 targets don't have a "cx_mem" region, set llc_mmio to NULL in that
case to avoid the IS_ERR() condition in a6xx_llc_activate().

Fixes: 3d247123 ("drm/msm/a6xx: Add support for using system cache on MMU500 based targets")
Signed-off-by: default avatarJonathan Marek <jonathan@marek.ca>
Link: https://lore.kernel.org/r/20210424014927.1661-1-jonathan@marek.ca


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 10f76165

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+5 −4
Original line number Diff line number Diff line
@@ -1153,10 +1153,6 @@ static void a6xx_llc_slices_init(struct platform_device *pdev, 
{

	struct device_node *phandle;



	a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem", "gpu_cx");

	if (IS_ERR(a6xx_gpu->llc_mmio))

		return;



	/*

	 * There is a different programming path for targets with an mmu500

	 * attached, so detect if that is the case
@@ -1166,6 +1162,11 @@ static void a6xx_llc_slices_init(struct platform_device *pdev, 
		of_device_is_compatible(phandle, "arm,mmu-500"));

	of_node_put(phandle);



	if (a6xx_gpu->have_mmu500)

		a6xx_gpu->llc_mmio = NULL;

	else

		a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem", "gpu_cx");



	a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);

	a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);