Commit 4b85d405 authored by Kuogee Hsieh's avatar Kuogee Hsieh Committed by Rob Clark
Browse files

drm/msm/dp: reduce link rate if failed at link training 1 



Reduce link rate and re start link training if link training 1
failed due to loss of clock recovery done to fix Link Layer
CTS case 4.3.1.7.  Also only update voltage and pre-emphasis
swing level after link training started to fix Link Layer CTS
case 4.3.1.6.

Changes in V2:
-- replaced cr_status with link_status[DP_LINK_STATUS_SIZE]
-- replaced dp_ctrl_any_lane_cr_done() with dp_ctrl_colco_recovery_any_ok()
-- replaced dp_ctrl_any_ane_cr_lose() with !drm_dp_clock_recovery_ok()

Changes in V3:
-- return failed if lane_count <= 1

Signed-off-by: default avatarKuogee Hsieh <khsieh@codeaurora.org>
Reviewed-by: default avatarStephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/1628196295-7382-3-git-send-email-khsieh@codeaurora.org


[remove unused cr_status variable]
Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 52352fe2

drivers/gpu/drm/msm/dp/dp_ctrl.c

+44 −34
Original line number Diff line number Diff line
@@ -81,13 +81,6 @@ struct dp_ctrl_private { 
	struct completion video_comp;

};



struct dp_cr_status {

	u8 lane_0_1;

	u8 lane_2_3;

};



#define DP_LANE0_1_CR_DONE	0x11



static int dp_aux_link_configure(struct drm_dp_aux *aux,

					struct dp_link_info *link)

{
@@ -1080,7 +1073,7 @@ static int dp_ctrl_read_link_status(struct dp_ctrl_private *ctrl, 
}



static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl,

		struct dp_cr_status *cr, int *training_step)

			int *training_step)

{

	int tries, old_v_level, ret = 0;

	u8 link_status[DP_LINK_STATUS_SIZE];
@@ -1109,9 +1102,6 @@ static int dp_ctrl_link_train_1(struct dp_ctrl_private *ctrl, 
		if (ret)

			return ret;



		cr->lane_0_1 = link_status[0];

		cr->lane_2_3 = link_status[1];



		if (drm_dp_clock_recovery_ok(link_status,

			ctrl->link->link_params.num_lanes)) {

			return 0;
@@ -1188,7 +1178,7 @@ static void dp_ctrl_clear_training_pattern(struct dp_ctrl_private *ctrl) 
}



static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl,

		struct dp_cr_status *cr, int *training_step)

			int *training_step)

{

	int tries = 0, ret = 0;

	char pattern;
@@ -1204,10 +1194,6 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, 
	else

		pattern = DP_TRAINING_PATTERN_2;



	ret = dp_ctrl_update_vx_px(ctrl);

	if (ret)

		return ret;



	ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, pattern);

	if (ret)

		return ret;
@@ -1220,8 +1206,6 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, 
		ret = dp_ctrl_read_link_status(ctrl, link_status);

		if (ret)

			return ret;

		cr->lane_0_1 = link_status[0];

		cr->lane_2_3 = link_status[1];



		if (drm_dp_channel_eq_ok(link_status,

			ctrl->link->link_params.num_lanes)) {
@@ -1241,7 +1225,7 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, 
static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl);



static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl,

		struct dp_cr_status *cr, int *training_step)

			int *training_step)

{

	int ret = 0;

	u8 encoding = DP_SET_ANSI_8B10B;
@@ -1257,7 +1241,7 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, 
	drm_dp_dpcd_write(ctrl->aux, DP_MAIN_LINK_CHANNEL_CODING_SET,

				&encoding, 1);



	ret = dp_ctrl_link_train_1(ctrl, cr, training_step);

	ret = dp_ctrl_link_train_1(ctrl, training_step);

	if (ret) {

		DRM_ERROR("link training #1 failed. ret=%d\n", ret);

		goto end;
@@ -1266,7 +1250,7 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, 
	/* print success info as this is a result of user initiated action */

	DRM_DEBUG_DP("link training #1 successful\n");



	ret = dp_ctrl_link_train_2(ctrl, cr, training_step);

	ret = dp_ctrl_link_train_2(ctrl, training_step);

	if (ret) {

		DRM_ERROR("link training #2 failed. ret=%d\n", ret);

		goto end;
@@ -1282,7 +1266,7 @@ static int dp_ctrl_link_train(struct dp_ctrl_private *ctrl, 
}



static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl,

		struct dp_cr_status *cr, int *training_step)

			int *training_step)

{

	int ret = 0;
@@ -1297,7 +1281,7 @@ static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl, 
	 * a link training pattern, we have to first do soft reset.

	 */



	ret = dp_ctrl_link_train(ctrl, cr, training_step);

	ret = dp_ctrl_link_train(ctrl, training_step);



	return ret;

}
@@ -1495,14 +1479,13 @@ static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl) 
static int dp_ctrl_link_maintenance(struct dp_ctrl_private *ctrl)

{

	int ret = 0;

	struct dp_cr_status cr;

	int training_step = DP_TRAINING_NONE;



	dp_ctrl_push_idle(&ctrl->dp_ctrl);



	ctrl->dp_ctrl.pixel_rate = ctrl->panel->dp_mode.drm_mode.clock;



	ret = dp_ctrl_setup_main_link(ctrl, &cr, &training_step);

	ret = dp_ctrl_setup_main_link(ctrl, &training_step);

	if (ret)

		goto end;
@@ -1633,6 +1616,25 @@ void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl) 
	}

}



static bool dp_ctrl_clock_recovery_any_ok(

			const u8 link_status[DP_LINK_STATUS_SIZE],

			int lane_count)

{

	int reduced_cnt;



	if (lane_count <= 1)

		return false;



	/*

	 * only interested in the lane number after reduced

	 * lane_count = 4, then only interested in 2 lanes

	 * lane_count = 2, then only interested in 1 lane

	 */

	reduced_cnt = lane_count >> 1;



	return drm_dp_clock_recovery_ok(link_status, reduced_cnt);

}



int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl)

{

	int rc = 0;
@@ -1640,7 +1642,7 @@ int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl) 
	u32 rate = 0;

	int link_train_max_retries = 5;

	u32 const phy_cts_pixel_clk_khz = 148500;

	struct dp_cr_status cr;

	u8 link_status[DP_LINK_STATUS_SIZE];

	unsigned int training_step;



	if (!dp_ctrl)
@@ -1680,19 +1682,21 @@ int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl) 
		}



		training_step = DP_TRAINING_NONE;

		rc = dp_ctrl_setup_main_link(ctrl, &cr, &training_step);

		rc = dp_ctrl_setup_main_link(ctrl, &training_step);

		if (rc == 0) {

			/* training completed successfully */

			break;

		} else if (training_step == DP_TRAINING_1) {

			/* link train_1 failed */

			if (!dp_catalog_link_is_connected(ctrl->catalog)) {

			if (!dp_catalog_link_is_connected(ctrl->catalog))

				break;

			}



			dp_ctrl_read_link_status(ctrl, link_status);



			rc = dp_ctrl_link_rate_down_shift(ctrl);

			if (rc < 0) { /* already in RBR = 1.6G */

				if (cr.lane_0_1 & DP_LANE0_1_CR_DONE) {

				if (dp_ctrl_clock_recovery_any_ok(link_status,

					ctrl->link->link_params.num_lanes)) {

					/*

					 * some lanes are ready,

					 * reduce lane number
@@ -1708,12 +1712,18 @@ int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl) 
				}

			}

		} else if (training_step == DP_TRAINING_2) {

			/* link train_2 failed, lower lane rate */

			if (!dp_catalog_link_is_connected(ctrl->catalog)) {

			/* link train_2 failed */

			if (!dp_catalog_link_is_connected(ctrl->catalog))

				break;

			}



			dp_ctrl_read_link_status(ctrl, link_status);



			if (!drm_dp_clock_recovery_ok(link_status,

					ctrl->link->link_params.num_lanes))

				rc = dp_ctrl_link_rate_down_shift(ctrl);

			else

				rc = dp_ctrl_link_lane_down_shift(ctrl);



			if (rc < 0) {

				/* end with failure */

				break; /* lane == 1 already */