Unverified Commit 4b740779 authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

Merge patch series "RISC-V: Apply Zicboz to clear_page" 

Andrew Jones <ajones@ventanamicro.com> says:

When the Zicboz extension is available we can more rapidly zero naturally
aligned Zicboz block sized chunks of memory. As pages are always page
aligned and are larger than any Zicboz block size will be, then
clear_page() appears to be a good candidate for the extension. While cycle
count and energy consumption should also be considered, we can be pretty
certain that implementing clear_page() with the Zicboz extension is a win
by comparing the new dynamic instruction count with its current count[1].
Doing so we see that the new count is just over a quarter of the old count
(see patch6's commit message for more details).

For those of you who reviewed v1[2], you may be looking for the memset()
patches. As pointed out in v1, and a couple follow-up emails, it's not
clear that patching memset() is a win yet. When I get a chance to test
on real hardware with a comprehensive benchmark collection then I can
post the memset() patches separately (assuming the benchmarks show it's
worthwhile).

* b4-shazam-merge:
  RISC-V: KVM: Expose Zicboz to the guest
  RISC-V: KVM: Provide UAPI for Zicboz block size
  RISC-V: Use Zicboz in clear_page when available
  RISC-V: cpufeatures: Put the upper 16 bits of patch ID to work
  RISC-V: Add Zicboz detection and block size parsing
  dt-bindings: riscv: Document cboz-block-size
  RISC-V: Factor out body of riscv_init_cbom_blocksize loop
  RISC-V: alternatives: Support patching multiple insns in assembly

Link: https://lore.kernel.org/r/20230224162631.405473-1-ajones@ventanamicro.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parents 73bde0ca b20f6799

Documentation/devicetree/bindings/riscv/cpus.yaml

+5 −0
Original line number Diff line number Diff line
@@ -72,6 +72,11 @@ properties: 
    description:

      The blocksize in bytes for the Zicbom cache operations.



  riscv,cboz-block-size:

    $ref: /schemas/types.yaml#/definitions/uint32

    description:

      The blocksize in bytes for the Zicboz cache operations.



  riscv,isa:

    description:

      Identifies the specific RISC-V instruction set architecture

arch/riscv/Kconfig

+13 −0
Original line number Diff line number Diff line
@@ -476,6 +476,19 @@ config RISCV_ISA_ZICBOM 


	   If you don't know what to do here, say Y.



config RISCV_ISA_ZICBOZ

	bool "Zicboz extension support for faster zeroing of memory"

	depends on !XIP_KERNEL && MMU

	select RISCV_ALTERNATIVE

	default y

	help

	   Enable the use of the ZICBOZ extension (cbo.zero instruction)

	   when available.



	   The Zicboz extension is used for faster zeroing of memory.



	   If you don't know what to do here, say Y.



config TOOLCHAIN_HAS_ZIHINTPAUSE

	bool

	default y

arch/riscv/include/asm/alternative-macros.h

+3 −3
Original line number Diff line number Diff line
@@ -14,7 +14,7 @@ 
	.4byte \patch_id

.endm



.macro ALT_NEW_CONTENT vendor_id, patch_id, enable = 1, new_c : vararg

.macro ALT_NEW_CONTENT vendor_id, patch_id, enable = 1, new_c

	.if \enable

	.pushsection .alternative, "a"

	ALT_ENTRY 886b, 888f, \vendor_id, \patch_id, 889f - 888f
@@ -41,13 +41,13 @@ 
	\old_c

	.option pop

887 :

	ALT_NEW_CONTENT \vendor_id, \patch_id, \enable, \new_c

	ALT_NEW_CONTENT \vendor_id, \patch_id, \enable, "\new_c"

.endm



.macro ALTERNATIVE_CFG_2 old_c, new_c_1, vendor_id_1, patch_id_1, enable_1,	\

				new_c_2, vendor_id_2, patch_id_2, enable_2

	ALTERNATIVE_CFG "\old_c", "\new_c_1", \vendor_id_1, \patch_id_1, \enable_1

	ALT_NEW_CONTENT \vendor_id_2, \patch_id_2, \enable_2, \new_c_2

	ALT_NEW_CONTENT \vendor_id_2, \patch_id_2, \enable_2, "\new_c_2"

.endm



#define __ALTERNATIVE_CFG(...)		ALTERNATIVE_CFG __VA_ARGS__

arch/riscv/include/asm/alternative.h

+4 −0
Original line number Diff line number Diff line
@@ -13,10 +13,14 @@ 
#ifdef CONFIG_RISCV_ALTERNATIVE



#include <linux/init.h>

#include <linux/kernel.h>

#include <linux/types.h>

#include <linux/stddef.h>

#include <asm/hwcap.h>



#define PATCH_ID_CPUFEATURE_ID(p)		lower_16_bits(p)

#define PATCH_ID_CPUFEATURE_VALUE(p)		upper_16_bits(p)



#define RISCV_ALTERNATIVES_BOOT		0 /* alternatives applied during regular boot */

#define RISCV_ALTERNATIVES_MODULE	1 /* alternatives applied during module-init */

#define RISCV_ALTERNATIVES_EARLY_BOOT	2 /* alternatives applied before mmu start */

arch/riscv/include/asm/cacheflush.h

+2 −1
Original line number Diff line number Diff line
@@ -50,7 +50,8 @@ void flush_icache_mm(struct mm_struct *mm, bool local); 
#endif /* CONFIG_SMP */



extern unsigned int riscv_cbom_block_size;

void riscv_init_cbom_blocksize(void);

extern unsigned int riscv_cboz_block_size;

void riscv_init_cbo_blocksizes(void);



#ifdef CONFIG_RISCV_DMA_NONCOHERENT

void riscv_noncoherent_supported(void);