Unverified Commit 4b72b10a authored by Maxime Ripard's avatar Maxime Ripard
Browse files

drm/vc4: crtc: Move HVS channel init before the PV initialisation 



In order to avoid stale pixels getting stuck in an intermediate FIFO
between the HVS and the pixelvalve on BCM2711, we need to configure the HVS
channel before the pixelvalve is reset and configured.

Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
Tested-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Tested-by: default avatarHoegeun Kwon <hoegeun.kwon@samsung.com>
Tested-by: default avatarStefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: default avatarDave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://patchwork.freedesktop.org/patch/msgid/9d7c5a03bc1a1e6d50f7b617cc2d8a46a4bbb7bc.1599120059.git-series.maxime@cerno.tech
parent 6370be84

drivers/gpu/drm/vc4/vc4_crtc.c

+4 −4
Original line number Diff line number Diff line
@@ -427,10 +427,6 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc, 


	require_hvs_enabled(dev);



	vc4_crtc_config_pv(crtc);



	CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);



	/* Enable vblank irq handling before crtc is started otherwise

	 * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().

	 */
@@ -438,6 +434,10 @@ static void vc4_crtc_atomic_enable(struct drm_crtc *crtc, 


	vc4_hvs_atomic_enable(crtc, old_state);



	vc4_crtc_config_pv(crtc);



	CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);



	/* When feeding the transposer block the pixelvalve is unneeded and

	 * should not be enabled.

	 */