Commit 4b5b9c7d authored by Shay Agroskin's avatar Shay Agroskin Committed by Saeed Mahameed
Browse files

net/mlx5: Add FEC fields to Port Phy Link Mode (PPLM) reg 



Added FEC related fields to PPLM layout.
These fields are needed to set and query FEC policy
for different link speeds.

Signed-off-by: default avatarShay Agroskin <shayag@mellanox.com>
Reviewed-by: default avatarEran Ben Elisha <eranbe@mellanox.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@mellanox.com>
parent 2a4c4298

include/linux/mlx5/driver.h

+1 −0
Original line number Diff line number Diff line
@@ -133,6 +133,7 @@ enum { 
	MLX5_REG_PVLC		 = 0x500f,

	MLX5_REG_PCMR		 = 0x5041,

	MLX5_REG_PMLP		 = 0x5002,

	MLX5_REG_PPLM		 = 0x5023,

	MLX5_REG_PCAM		 = 0x507f,

	MLX5_REG_NODE_DESC	 = 0x6001,

	MLX5_REG_HOST_ENDIANNESS = 0x7004,

include/linux/mlx5/mlx5_ifc.h

+28 −11
Original line number Diff line number Diff line
@@ -7841,7 +7841,21 @@ struct mlx5_ifc_pplm_reg_bits { 
	u8	   retransmission_active[0x8];

	u8	   fec_mode_active[0x18];



	u8         reserved_at_80[0x20];

	u8	   rs_fec_correction_bypass_cap[0x4];

	u8	   reserved_at_84[0x8];

	u8	   fec_override_cap_56g[0x4];

	u8	   fec_override_cap_100g[0x4];

	u8	   fec_override_cap_50g[0x4];

	u8	   fec_override_cap_25g[0x4];

	u8	   fec_override_cap_10g_40g[0x4];



	u8	   rs_fec_correction_bypass_admin[0x4];

	u8	   reserved_at_a4[0x8];

	u8	   fec_override_admin_56g[0x4];

	u8	   fec_override_admin_100g[0x4];

	u8	   fec_override_admin_50g[0x4];

	u8	   fec_override_admin_25g[0x4];

	u8	   fec_override_admin_10g_40g[0x4];

};



struct mlx5_ifc_ppcnt_reg_bits {
@@ -8137,7 +8151,10 @@ struct mlx5_ifc_pcam_enhanced_features_bits { 
struct mlx5_ifc_pcam_regs_5000_to_507f_bits {

	u8         port_access_reg_cap_mask_127_to_96[0x20];

	u8         port_access_reg_cap_mask_95_to_64[0x20];

	u8         port_access_reg_cap_mask_63_to_32[0x20];



	u8         port_access_reg_cap_mask_63_to_36[0x1c];

	u8         pplm[0x1];

	u8         port_access_reg_cap_mask_34_to_32[0x3];



	u8         port_access_reg_cap_mask_31_to_13[0x13];

	u8         pbmc[0x1];