Commit 4b5a3ab1 authored by Srujana Challa's avatar Srujana Challa Committed by David S. Miller
Browse files

octeontx2-af: Hardware configuration for inline IPsec 



On OcteonTX2/CN10K SoC, the admin function (AF) is the only one
with all priviliges to configure HW and alloc resources, PFs and
it's VFs have to request AF via mailbox for all their needs.
This patch adds new mailbox messages for CPT PFs and VFs to configure
HW resources for inline-IPsec.

Signed-off-by: default avatarSubbaraya Sundeep <sbhatta@marvell.com>
Signed-off-by: default avatarSrujana Challa <schalla@marvell.com>
Signed-off-by: default avatarVidya Sagar Velumuri <vvelumuri@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 227b9644

drivers/net/ethernet/marvell/octeontx2/af/common.h

+1 −0
Original line number Diff line number Diff line
@@ -191,6 +191,7 @@ enum nix_scheduler { 
#define NIX_CHAN_SDP_CH_START          (0x700ull)

#define NIX_CHAN_SDP_CHX(a)            (NIX_CHAN_SDP_CH_START + (a))

#define NIX_CHAN_SDP_NUM_CHANS		256

#define NIX_CHAN_CPT_CH_START          (0x800ull)



/* The mask is to extract lower 10-bits of channel number

 * which CPT will pass to X2P.

drivers/net/ethernet/marvell/octeontx2/af/mbox.h

+59 −1
Original line number Diff line number Diff line
@@ -186,6 +186,8 @@ M(CPT_LF_ALLOC, 0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg, \ 
M(CPT_LF_FREE,		0xA01, cpt_lf_free, msg_req, msg_rsp)		\

M(CPT_RD_WR_REGISTER,	0xA02, cpt_rd_wr_register,  cpt_rd_wr_reg_msg,	\

			       cpt_rd_wr_reg_msg)			\

M(CPT_INLINE_IPSEC_CFG,	0xA04, cpt_inline_ipsec_cfg,			\

			       cpt_inline_ipsec_cfg_msg, msg_rsp)	\

M(CPT_STATS,            0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp)	\

M(CPT_RXC_TIME_CFG,     0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req,  \

			       msg_rsp)                                 \
@@ -270,6 +272,10 @@ M(NIX_BP_ENABLE, 0x8016, nix_bp_enable, nix_bp_cfg_req, \ 
				nix_bp_cfg_rsp)	\

M(NIX_BP_DISABLE,	0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \

M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \

M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg,			\

				nix_inline_ipsec_cfg, msg_rsp)		\

M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg,		\

				nix_inline_ipsec_lf_cfg, msg_rsp)	\

M(NIX_CN10K_AQ_ENQ,	0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \

				nix_cn10k_aq_enq_rsp)			\

M(NIX_GET_HW_INFO,	0x801c, nix_get_hw_info, msg_req, nix_hw_info)	\
@@ -1065,6 +1071,40 @@ struct nix_bp_cfg_rsp { 
	u8	chan_cnt; /* Number of channel for which bpids are assigned */

};



/* Global NIX inline IPSec configuration */

struct nix_inline_ipsec_cfg {

	struct mbox_msghdr hdr;

	u32 cpt_credit;

	struct {

		u8 egrp;

		u8 opcode;

		u16 param1;

		u16 param2;

	} gen_cfg;

	struct {

		u16 cpt_pf_func;

		u8 cpt_slot;

	} inst_qsel;

	u8 enable;

};



/* Per NIX LF inline IPSec configuration */

struct nix_inline_ipsec_lf_cfg {

	struct mbox_msghdr hdr;

	u64 sa_base_addr;

	struct {

		u32 tag_const;

		u16 lenm1_max;

		u8 sa_pow2_size;

		u8 tt;

	} ipsec_cfg0;

	struct {

		u32 sa_idx_max;

		u8 sa_idx_w;

	} ipsec_cfg1;

	u8 enable;

};



struct nix_hw_info {

	struct mbox_msghdr hdr;

	u16 rsvs16;
@@ -1399,7 +1439,9 @@ enum cpt_af_status { 
	CPT_AF_ERR_LF_INVALID		= -903,

	CPT_AF_ERR_ACCESS_DENIED	= -904,

	CPT_AF_ERR_SSO_PF_FUNC_INVALID	= -905,

	CPT_AF_ERR_NIX_PF_FUNC_INVALID	= -906

	CPT_AF_ERR_NIX_PF_FUNC_INVALID	= -906,

	CPT_AF_ERR_INLINE_IPSEC_INB_ENA	= -907,

	CPT_AF_ERR_INLINE_IPSEC_OUT_ENA	= -908

};



/* CPT mbox message formats */
@@ -1420,6 +1462,22 @@ struct cpt_lf_alloc_req_msg { 
	int blkaddr;

};



#define CPT_INLINE_INBOUND      0

#define CPT_INLINE_OUTBOUND     1



/* Mailbox message request format for CPT IPsec

 * inline inbound and outbound configuration.

 */

struct cpt_inline_ipsec_cfg_msg {

	struct mbox_msghdr hdr;

	u8 enable;

	u8 slot;

	u8 dir;

	u8 sso_pf_func_ovrd;

	u16 sso_pf_func; /* inbound path SSO_PF_FUNC */

	u16 nix_pf_func; /* outbound path NIX_PF_FUNC */

};



/* Mailbox message request and response format for CPT stats. */

struct cpt_sts_req {

	struct mbox_msghdr hdr;

drivers/net/ethernet/marvell/octeontx2/af/rvu.c

+54 −0
Original line number Diff line number Diff line
@@ -1287,6 +1287,60 @@ static int rvu_lookup_rsrc(struct rvu *rvu, struct rvu_block *block, 
	return (val & 0xFFF);

}



int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc,

			      u16 global_slot, u16 *slot_in_block)

{

	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);

	int numlfs, total_lfs = 0, nr_blocks = 0;

	int i, num_blkaddr[BLK_COUNT] = { 0 };

	struct rvu_block *block;

	int blkaddr = -ENODEV;

	u16 start_slot;



	if (!is_blktype_attached(pfvf, blktype))

		return -ENODEV;



	/* Get all the block addresses from which LFs are attached to

	 * the given pcifunc in num_blkaddr[].

	 */

	for (blkaddr = BLKADDR_RVUM; blkaddr < BLK_COUNT; blkaddr++) {

		block = &rvu->hw->block[blkaddr];

		if (block->type != blktype)

			continue;

		if (!is_block_implemented(rvu->hw, blkaddr))

			continue;



		numlfs = rvu_get_rsrc_mapcount(pfvf, blkaddr);

		if (numlfs) {

			total_lfs += numlfs;

			num_blkaddr[nr_blocks] = blkaddr;

			nr_blocks++;

		}

	}



	if (global_slot >= total_lfs)

		return -ENODEV;



	/* Based on the given global slot number retrieve the

	 * correct block address out of all attached block

	 * addresses and slot number in that block.

	 */

	total_lfs = 0;

	blkaddr = -ENODEV;

	for (i = 0; i < nr_blocks; i++) {

		numlfs = rvu_get_rsrc_mapcount(pfvf, num_blkaddr[i]);

		total_lfs += numlfs;

		if (global_slot < total_lfs) {

			blkaddr = num_blkaddr[i];

			start_slot = total_lfs - numlfs;

			*slot_in_block = global_slot - start_slot;

			break;

		}

	}



	return blkaddr;

}



static void rvu_detach_block(struct rvu *rvu, int pcifunc, int blktype)

{

	struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc);

drivers/net/ethernet/marvell/octeontx2/af/rvu.h

+2 −0
Original line number Diff line number Diff line
@@ -656,6 +656,8 @@ int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf); 
int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);

int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);

int rvu_get_num_lbk_chans(void);

int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc,

			      u16 global_slot, u16 *slot_in_block);



/* RVU HW reg validation */

enum regmap_block {

drivers/net/ethernet/marvell/octeontx2/af/rvu_cn10k.c

+2 −2
Original line number Diff line number Diff line
@@ -334,8 +334,8 @@ int rvu_set_channels_base(struct rvu *rvu) 
	/* Out of 4096 channels start CPT from 2048 so

	 * that MSB for CPT channels is always set

	 */

	if (cpt_chan_base <= 0x800) {

		hw->cpt_chan_base = 0x800;

	if (cpt_chan_base <= NIX_CHAN_CPT_CH_START) {

		hw->cpt_chan_base = NIX_CHAN_CPT_CH_START;

	} else {

		dev_err(rvu->dev,

			"CPT channels could not fit in the range 2048-4095\n");