dt-bindings: display/msm: add missing device nodes to mdss-* schemas (4b32e466) · Commits · EulixOS / Software / Kernel

Documentation/devicetree/bindings/display/msm/qcom,msm8998-mdss.yaml

+153 −0

Original line number	Diff line number	Diff line
		@@ -43,11 +43,24 @@ patternProperties:
		compatible:
		const: qcom,msm8998-dpu

		"^dsi@[0-9a-f]+$":
		type: object
		properties:
		compatible:
		const: qcom,mdss-dsi-ctrl

		"^phy@[0-9a-f]+$":
		type: object
		properties:
		compatible:
		const: qcom,dsi-phy-10nm-8998

		unevaluatedProperties: false

		examples:
		- \|
		#include <dt-bindings/clock/qcom,mmcc-msm8998.h>
		#include <dt-bindings/clock/qcom,rpmcc.h>
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		#include <dt-bindings/power/qcom-rpmpd.h>

		@@ -111,5 +124,145 @@ examples:
		};
		};
		};

		dsi@c994000 {
		compatible = "qcom,mdss-dsi-ctrl";
		reg = <0x0c994000 0x400>;
		reg-names = "dsi_ctrl";

		interrupt-parent = <&mdss>;
		interrupts = <4>;

		clocks = <&mmcc MDSS_BYTE0_CLK>,
		<&mmcc MDSS_BYTE0_INTF_CLK>,
		<&mmcc MDSS_PCLK0_CLK>,
		<&mmcc MDSS_ESC0_CLK>,
		<&mmcc MDSS_AHB_CLK>,
		<&mmcc MDSS_AXI_CLK>;
		clock-names = "byte",
		"byte_intf",
		"pixel",
		"core",
		"iface",
		"bus";
		assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
		assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;

		operating-points-v2 = <&dsi_opp_table>;
		power-domains = <&rpmpd MSM8998_VDDCX>;

		phys = <&dsi0_phy>;
		phy-names = "dsi";

		#address-cells = <1>;
		#size-cells = <0>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		dsi0_in: endpoint {
		remote-endpoint = <&dpu_intf1_out>;
		};
		};

		port@1 {
		reg = <1>;
		dsi0_out: endpoint {
		};
		};
		};
		};

		dsi0_phy: phy@c994400 {
		compatible = "qcom,dsi-phy-10nm-8998";
		reg = <0x0c994400 0x200>,
		<0x0c994600 0x280>,
		<0x0c994a00 0x1e0>;
		reg-names = "dsi_phy",
		"dsi_phy_lane",
		"dsi_pll";

		#clock-cells = <1>;
		#phy-cells = <0>;

		clocks = <&mmcc MDSS_AHB_CLK>,
		<&rpmcc RPM_SMD_XO_CLK_SRC>;
		clock-names = "iface", "ref";

		vdds-supply = <&pm8998_l1>;
		};

		dsi@c996000 {
		compatible = "qcom,mdss-dsi-ctrl";
		reg = <0x0c996000 0x400>;
		reg-names = "dsi_ctrl";

		interrupt-parent = <&mdss>;
		interrupts = <5>;

		clocks = <&mmcc MDSS_BYTE1_CLK>,
		<&mmcc MDSS_BYTE1_INTF_CLK>,
		<&mmcc MDSS_PCLK1_CLK>,
		<&mmcc MDSS_ESC1_CLK>,
		<&mmcc MDSS_AHB_CLK>,
		<&mmcc MDSS_AXI_CLK>;
		clock-names = "byte",
		"byte_intf",
		"pixel",
		"core",
		"iface",
		"bus";
		assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
		assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;

		operating-points-v2 = <&dsi_opp_table>;
		power-domains = <&rpmpd MSM8998_VDDCX>;

		phys = <&dsi1_phy>;
		phy-names = "dsi";

		#address-cells = <1>;
		#size-cells = <0>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		dsi1_in: endpoint {
		remote-endpoint = <&dpu_intf2_out>;
		};
		};

		port@1 {
		reg = <1>;
		dsi1_out: endpoint {
		};
		};
		};
		};

		dsi1_phy: phy@c996400 {
		compatible = "qcom,dsi-phy-10nm-8998";
		reg = <0x0c996400 0x200>,
		<0x0c996600 0x280>,
		<0x0c996a00 0x10e>;
		reg-names = "dsi_phy",
		"dsi_phy_lane",
		"dsi_pll";

		#clock-cells = <1>;
		#phy-cells = <0>;

		clocks = <&mmcc MDSS_AHB_CLK>,
		<&rpmcc RPM_SMD_XO_CLK_SRC>;
		clock-names = "iface", "ref";

		vdds-supply = <&pm8998_l1>;
		};
		};
		...

Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml

+81 −0

Original line number	Diff line number	Diff line
		@@ -49,12 +49,25 @@ patternProperties:
		compatible:
		const: qcom,qcm2290-dpu

		"^dsi@[0-9a-f]+$":
		type: object
		properties:
		compatible:
		const: qcom,dsi-ctrl-6g-qcm2290

		"^phy@[0-9a-f]+$":
		type: object
		properties:
		compatible:
		const: qcom,dsi-phy-14nm-2290

		unevaluatedProperties: false

		examples:
		- \|
		#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
		#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
		#include <dt-bindings/clock/qcom,rpmcc.h>
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		#include <dt-bindings/interconnect/qcom,qcm2290.h>
		#include <dt-bindings/power/qcom-rpmpd.h>
		@@ -113,5 +126,73 @@ examples:
		};
		};
		};

		dsi@5e94000 {
		compatible = "qcom,dsi-ctrl-6g-qcm2290";
		reg = <0x05e94000 0x400>;
		reg-names = "dsi_ctrl";

		interrupt-parent = <&mdss>;
		interrupts = <4>;

		clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
		<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
		<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
		<&dispcc DISP_CC_MDSS_ESC0_CLK>,
		<&dispcc DISP_CC_MDSS_AHB_CLK>,
		<&gcc GCC_DISP_HF_AXI_CLK>;
		clock-names = "byte",
		"byte_intf",
		"pixel",
		"core",
		"iface",
		"bus";
		assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
		assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;

		operating-points-v2 = <&dsi_opp_table>;
		power-domains = <&rpmpd QCM2290_VDDCX>;

		phys = <&dsi0_phy>;
		phy-names = "dsi";

		#address-cells = <1>;
		#size-cells = <0>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		dsi0_in: endpoint {
		remote-endpoint = <&dpu_intf1_out>;
		};
		};

		port@1 {
		reg = <1>;
		dsi0_out: endpoint {
		};
		};
		};
		};

		dsi0_phy: phy@5e94400 {
		compatible = "qcom,dsi-phy-14nm-2290";
		reg = <0x05e94400 0x100>,
		<0x05e94500 0x300>,
		<0x05e94800 0x188>;
		reg-names = "dsi_phy",
		"dsi_phy_lane",
		"dsi_pll";

		#clock-cells = <1>;
		#phy-cells = <0>;

		clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
		clock-names = "iface", "ref";
		vcca-supply = <&vreg_dsi_phy>;
		};
		};
		...

Documentation/devicetree/bindings/display/msm/qcom,sc7180-mdss.yaml

+179 −0

Original line number	Diff line number	Diff line
		@@ -49,12 +49,31 @@ patternProperties:
		compatible:
		const: qcom,sc7180-dpu

		"^displayport-controller@[0-9a-f]+$":
		type: object
		properties:
		compatible:
		const: qcom,sc7180-dp

		"^dsi@[0-9a-f]+$":
		type: object
		properties:
		compatible:
		const: qcom,mdss-dsi-ctrl

		"^phy@[0-9a-f]+$":
		type: object
		properties:
		compatible:
		const: qcom,dsi-phy-10nm

		unevaluatedProperties: false

		examples:
		- \|
		#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
		#include <dt-bindings/clock/qcom,gcc-sc7180.h>
		#include <dt-bindings/clock/qcom,rpmh.h>
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		#include <dt-bindings/interconnect/qcom,sdm845.h>
		#include <dt-bindings/power/qcom-rpmpd.h>
		@@ -121,5 +140,165 @@ examples:
		};
		};
		};

		dsi@ae94000 {
		compatible = "qcom,mdss-dsi-ctrl";
		reg = <0x0ae94000 0x400>;
		reg-names = "dsi_ctrl";

		interrupt-parent = <&mdss>;
		interrupts = <4>;

		clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
		<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
		<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
		<&dispcc DISP_CC_MDSS_ESC0_CLK>,
		<&dispcc DISP_CC_MDSS_AHB_CLK>,
		<&gcc GCC_DISP_HF_AXI_CLK>;
		clock-names = "byte",
		"byte_intf",
		"pixel",
		"core",
		"iface",
		"bus";

		assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
		assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;

		operating-points-v2 = <&dsi_opp_table>;
		power-domains = <&rpmhpd SC7180_CX>;

		phys = <&dsi_phy>;
		phy-names = "dsi";

		#address-cells = <1>;
		#size-cells = <0>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		dsi0_in: endpoint {
		remote-endpoint = <&dpu_intf1_out>;
		};
		};

		port@1 {
		reg = <1>;
		dsi0_out: endpoint {
		};
		};
		};

		dsi_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-187500000 {
		opp-hz = /bits/ 64 <187500000>;
		required-opps = <&rpmhpd_opp_low_svs>;
		};

		opp-300000000 {
		opp-hz = /bits/ 64 <300000000>;
		required-opps = <&rpmhpd_opp_svs>;
		};

		opp-358000000 {
		opp-hz = /bits/ 64 <358000000>;
		required-opps = <&rpmhpd_opp_svs_l1>;
		};
		};
		};

		dsi_phy: phy@ae94400 {
		compatible = "qcom,dsi-phy-10nm";
		reg = <0x0ae94400 0x200>,
		<0x0ae94600 0x280>,
		<0x0ae94a00 0x1e0>;
		reg-names = "dsi_phy",
		"dsi_phy_lane",
		"dsi_pll";

		#clock-cells = <1>;
		#phy-cells = <0>;

		clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
		<&rpmhcc RPMH_CXO_CLK>;
		clock-names = "iface", "ref";
		vdds-supply = <&vreg_dsi_phy>;
		};

		displayport-controller@ae90000 {
		compatible = "qcom,sc7180-dp";

		reg = <0xae90000 0x200>,
		<0xae90200 0x200>,
		<0xae90400 0xc00>,
		<0xae91000 0x400>,
		<0xae91400 0x400>;

		interrupt-parent = <&mdss>;
		interrupts = <12>;

		clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
		<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
		<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
		<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
		<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
		clock-names = "core_iface", "core_aux", "ctrl_link",
		"ctrl_link_iface", "stream_pixel";
		assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
		<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
		assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
		phys = <&dp_phy>;
		phy-names = "dp";

		operating-points-v2 = <&dp_opp_table>;
		power-domains = <&rpmhpd SC7180_CX>;

		#sound-dai-cells = <0>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
		reg = <0>;
		dp_in: endpoint {
		remote-endpoint = <&dpu_intf0_out>;
		};
		};

		port@1 {
		reg = <1>;
		dp_out: endpoint { };
		};
		};

		dp_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-160000000 {
		opp-hz = /bits/ 64 <160000000>;
		required-opps = <&rpmhpd_opp_low_svs>;
		};

		opp-270000000 {
		opp-hz = /bits/ 64 <270000000>;
		required-opps = <&rpmhpd_opp_svs>;
		};

		opp-540000000 {
		opp-hz = /bits/ 64 <540000000>;
		required-opps = <&rpmhpd_opp_svs_l1>;
		};

		opp-810000000 {
		opp-hz = /bits/ 64 <810000000>;
		required-opps = <&rpmhpd_opp_nom>;
		};
		};
		};
		};
		...

Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml

+292 −0

Original line number	Diff line number	Diff line
		@@ -48,12 +48,39 @@ patternProperties:
		compatible:
		const: qcom,sc7280-dpu

		"^displayport-controller@[0-9a-f]+$":
		type: object
		properties:
		compatible:
		const: qcom,sc7280-dp

		"^dsi@[0-9a-f]+$":
		type: object
		properties:
		compatible:
		const: qcom,mdss-dsi-ctrl

		"^edp@[0-9a-f]+$":
		type: object
		properties:
		compatible:
		const: qcom,sc7280-edp

		"^phy@[0-9a-f]+$":
		type: object
		properties:
		compatible:
		enum:
		- qcom,sc7280-dsi-phy-7nm
		- qcom,sc7280-edp-phy

		unevaluatedProperties: false

		examples:
		- \|
		#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
		#include <dt-bindings/clock/qcom,gcc-sc7280.h>
		#include <dt-bindings/clock/qcom,rpmh.h>
		#include <dt-bindings/interrupt-controller/arm-gic.h>
		#include <dt-bindings/interconnect/qcom,sc7280.h>
		#include <dt-bindings/power/qcom-rpmpd.h>
		@@ -124,6 +151,271 @@ examples:
		remote-endpoint = <&edp_in>;
		};
		};

		port@2 {
		reg = <2>;
		dpu_intf0_out: endpoint {
		remote-endpoint = <&dp_in>;
		};
		};
		};
		};

		dsi@ae94000 {
		compatible = "qcom,mdss-dsi-ctrl";
		reg = <0x0ae94000 0x400>;
		reg-names = "dsi_ctrl";

		interrupt-parent = <&mdss>;
		interrupts = <4>;

		clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
		<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
		<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
		<&dispcc DISP_CC_MDSS_ESC0_CLK>,
		<&dispcc DISP_CC_MDSS_AHB_CLK>,
		<&gcc GCC_DISP_HF_AXI_CLK>;
		clock-names = "byte",
		"byte_intf",
		"pixel",
		"core",
		"iface",
		"bus";

		assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
		<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
		assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;

		operating-points-v2 = <&dsi_opp_table>;
		power-domains = <&rpmhpd SC7280_CX>;

		phys = <&mdss_dsi_phy>;
		phy-names = "dsi";

		#address-cells = <1>;
		#size-cells = <0>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		dsi0_in: endpoint {
		remote-endpoint = <&dpu_intf1_out>;
		};
		};

		port@1 {
		reg = <1>;
		dsi0_out: endpoint {
		};
		};
		};

		dsi_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-187500000 {
		opp-hz = /bits/ 64 <187500000>;
		required-opps = <&rpmhpd_opp_low_svs>;
		};

		opp-300000000 {
		opp-hz = /bits/ 64 <300000000>;
		required-opps = <&rpmhpd_opp_svs>;
		};

		opp-358000000 {
		opp-hz = /bits/ 64 <358000000>;
		required-opps = <&rpmhpd_opp_svs_l1>;
		};
		};
		};

		mdss_dsi_phy: phy@ae94400 {
		compatible = "qcom,sc7280-dsi-phy-7nm";
		reg = <0x0ae94400 0x200>,
		<0x0ae94600 0x280>,
		<0x0ae94900 0x280>;
		reg-names = "dsi_phy",
		"dsi_phy_lane",
		"dsi_pll";

		#clock-cells = <1>;
		#phy-cells = <0>;

		clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
		<&rpmhcc RPMH_CXO_CLK>;
		clock-names = "iface", "ref";

		vdds-supply = <&vreg_dsi_supply>;
		};

		edp@aea0000 {
		compatible = "qcom,sc7280-edp";
		pinctrl-names = "default";
		pinctrl-0 = <&edp_hot_plug_det>;

		reg = <0xaea0000 0x200>,
		<0xaea0200 0x200>,
		<0xaea0400 0xc00>,
		<0xaea1000 0x400>;

		interrupt-parent = <&mdss>;
		interrupts = <14>;

		clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
		<&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
		<&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
		<&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
		<&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
		clock-names = "core_iface",
		"core_aux",
		"ctrl_link",
		"ctrl_link_iface",
		"stream_pixel";
		assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
		<&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
		assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;

		phys = <&mdss_edp_phy>;
		phy-names = "dp";

		operating-points-v2 = <&edp_opp_table>;
		power-domains = <&rpmhpd SC7280_CX>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		edp_in: endpoint {
		remote-endpoint = <&dpu_intf5_out>;
		};
		};

		port@1 {
		reg = <1>;
		mdss_edp_out: endpoint { };
		};
		};

		edp_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-160000000 {
		opp-hz = /bits/ 64 <160000000>;
		required-opps = <&rpmhpd_opp_low_svs>;
		};

		opp-270000000 {
		opp-hz = /bits/ 64 <270000000>;
		required-opps = <&rpmhpd_opp_svs>;
		};

		opp-540000000 {
		opp-hz = /bits/ 64 <540000000>;
		required-opps = <&rpmhpd_opp_nom>;
		};

		opp-810000000 {
		opp-hz = /bits/ 64 <810000000>;
		required-opps = <&rpmhpd_opp_nom>;
		};
		};
		};

		mdss_edp_phy: phy@aec2a00 {
		compatible = "qcom,sc7280-edp-phy";

		reg = <0xaec2a00 0x19c>,
		<0xaec2200 0xa0>,
		<0xaec2600 0xa0>,
		<0xaec2000 0x1c0>;

		clocks = <&rpmhcc RPMH_CXO_CLK>,
		<&gcc GCC_EDP_CLKREF_EN>;
		clock-names = "aux",
		"cfg_ahb";

		#clock-cells = <1>;
		#phy-cells = <0>;
		};

		displayport-controller@ae90000 {
		compatible = "qcom,sc7280-dp";

		reg = <0xae90000 0x200>,
		<0xae90200 0x200>,
		<0xae90400 0xc00>,
		<0xae91000 0x400>,
		<0xae91400 0x400>;

		interrupt-parent = <&mdss>;
		interrupts = <12>;

		clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
		<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
		<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
		<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
		<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
		clock-names = "core_iface",
		"core_aux",
		"ctrl_link",
		"ctrl_link_iface",
		"stream_pixel";
		assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
		<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
		assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
		phys = <&dp_phy>;
		phy-names = "dp";

		operating-points-v2 = <&dp_opp_table>;
		power-domains = <&rpmhpd SC7280_CX>;

		#sound-dai-cells = <0>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;

		port@0 {
		reg = <0>;
		dp_in: endpoint {
		remote-endpoint = <&dpu_intf0_out>;
		};
		};

		port@1 {
		reg = <1>;
		dp_out: endpoint { };
		};
		};

		dp_opp_table: opp-table {
		compatible = "operating-points-v2";

		opp-160000000 {
		opp-hz = /bits/ 64 <160000000>;
		required-opps = <&rpmhpd_opp_low_svs>;
		};

		opp-270000000 {
		opp-hz = /bits/ 64 <270000000>;
		required-opps = <&rpmhpd_opp_svs>;
		};

		opp-540000000 {
		opp-hz = /bits/ 64 <540000000>;
		required-opps = <&rpmhpd_opp_svs_l1>;
		};

		opp-810000000 {
		opp-hz = /bits/ 64 <810000000>;
		required-opps = <&rpmhpd_opp_nom>;
		};
		};
		};
		};

Documentation/devicetree/bindings/display/msm/qcom,sdm845-mdss.yaml

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