Commit 4b2c5fa9 authored by Amir Tzin's avatar Amir Tzin Committed by Saeed Mahameed
Browse files

net/mlx5: Add layout to support default timeouts register 



Add needed structures and defines for DTOR (default timeouts register).
This will be used to get timeouts values from FW instead of hard coded
values in the driver code thus enabling support for slower devices which
need longer timeouts.

Signed-off-by: default avatarAmir Tzin <amirtz@nvidia.com>
Reviewed-by: default avatarMoshe Shemesh <moshe@nvidia.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
parent 295711fa

include/linux/mlx5/device.h

+3 −1
Original line number Diff line number Diff line
@@ -577,7 +577,9 @@ struct mlx5_init_seg { 
	__be32			rsvd1[120];

	__be32			initializing;

	struct health_buffer	health;

	__be32			rsvd2[880];

	__be32			rsvd2[878];

	__be32			cmd_exec_to;

	__be32			cmd_q_init_to;

	__be32			internal_timer_h;

	__be32			internal_timer_l;

	__be32			rsvd3[2];

include/linux/mlx5/driver.h

+1 −0
Original line number Diff line number Diff line
@@ -156,6 +156,7 @@ enum { 
	MLX5_REG_MIRC		 = 0x9162,

	MLX5_REG_SBCAM		 = 0xB01F,

	MLX5_REG_RESOURCE_DUMP   = 0xC000,

	MLX5_REG_DTOR            = 0xC00E,

};



enum mlx5_qpts_trust_state {

include/linux/mlx5/mlx5_ifc.h

+36 −1
Original line number Diff line number Diff line
@@ -1306,7 +1306,8 @@ struct mlx5_ifc_cmd_hca_cap_bits { 
	u8         vhca_resource_manager[0x1];



	u8         hca_cap_2[0x1];

	u8         reserved_at_21[0x2];

	u8         reserved_at_21[0x1];

	u8         dtor[0x1];

	u8         event_on_vhca_state_teardown_request[0x1];

	u8         event_on_vhca_state_in_use[0x1];

	u8         event_on_vhca_state_active[0x1];
@@ -2807,6 +2808,40 @@ struct mlx5_ifc_dropped_packet_logged_bits { 
	u8         reserved_at_0[0xe0];

};



struct mlx5_ifc_default_timeout_bits {

	u8         to_multiplier[0x3];

	u8         reserved_at_3[0x9];

	u8         to_value[0x14];

};



struct mlx5_ifc_dtor_reg_bits {

	u8         reserved_at_0[0x20];



	struct mlx5_ifc_default_timeout_bits pcie_toggle_to;



	u8         reserved_at_40[0x60];



	struct mlx5_ifc_default_timeout_bits health_poll_to;



	struct mlx5_ifc_default_timeout_bits full_crdump_to;



	struct mlx5_ifc_default_timeout_bits fw_reset_to;



	struct mlx5_ifc_default_timeout_bits flush_on_err_to;



	struct mlx5_ifc_default_timeout_bits pci_sync_update_to;



	struct mlx5_ifc_default_timeout_bits tear_down_to;



	struct mlx5_ifc_default_timeout_bits fsm_reactivate_to;



	struct mlx5_ifc_default_timeout_bits reclaim_pages_to;



	struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to;



	u8         reserved_at_1c0[0x40];

};



enum {

	MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN                 = 0x1,

	MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR  = 0x2,