Commit 4b0253be authored by hanliyang's avatar hanliyang
Browse files

x86/cpufeatures: Add CPUID_8C86_0000_EDX CPUID leaf 

hygon inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I98NP1


CVE: NA

---------------------------

This is a pure feature bits leaf. Add SM3 and SM4 feature bits from
this leaf on Hygon CPUs.

Signed-off-by: default avatarhanliyang <hanliyang@hygon.cn>
parent 62f520bc

arch/x86/include/asm/cpufeature.h

+1 −1
Original line number Diff line number Diff line
@@ -43,7 +43,7 @@ enum cpuid_leafs 
	CPUID_RESERVED_6,

	CPUID_RESERVED_7,

	CPUID_RESERVED_8,

	CPUID_RESERVED_9,

	CPUID_8C86_0000_EDX,

	CPUID_C000_0006_EAX,

};

arch/x86/include/asm/cpufeatures.h

+4 −0
Original line number Diff line number Diff line
@@ -487,6 +487,10 @@ 
#define X86_FEATURE_CLEAR_BHB_HW	(21*32+ 3) /* "" BHI_DIS_S HW control enabled */

#define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* "" Clear branch history at vmexit using SW loop */



/* HYGON-defined CPU features, CPUID level 0x8c860000:0 (EDX), word 29 */

#define X86_FEATURE_SM3			(29*32 + 1) /* SM3 instructions */

#define X86_FEATURE_SM4			(29*32 + 2) /* SM4 instructions */



/* VIA/Cyrix/Centaur/Zhaoxin-defined CPU features, CPUID level 0xC0000006, word 21 */

#define X86_FEATURE_ZXPAUSE		(30*32 + 0) /* Zhaoxin ZXPAUSE */

arch/x86/kernel/cpu/hygon.c

+14 −0
Original line number Diff line number Diff line
@@ -246,6 +246,18 @@ static void bsp_init_hygon(struct cpuinfo_x86 *c) 
	resctrl_cpu_detect(c);

}



static void init_hygon_cap(struct cpuinfo_x86 *c)

{

	/* Test for Extended Feature Flags presence */

	if (cpuid_eax(0x8C860000) >= 0x8C860000) {

		/*

		 * Store Extended Feature Flags of the CPU capability

		 * bit array

		 */

		c->x86_capability[CPUID_8C86_0000_EDX] = cpuid_edx(0x8C860000);

	}

}



static void early_detect_mem_encrypt(struct cpuinfo_x86 *c)

{

	u64 msr;
@@ -401,6 +413,8 @@ static void init_hygon(struct cpuinfo_x86 *c) 


	/* Hygon CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */

	clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);



	init_hygon_cap(c);

}



static void cpu_detect_tlb_hygon(struct cpuinfo_x86 *c)