Commit 4afd2a93 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-ingenic' and 'clk-mediatek' into clk-next

 - Add MDMA and BDMA clks to Ingenic JZ4760 and JZ4770
 - MediaTek mt7986 SoC basic support

* clk-ingenic:
  clk: ingenic: Add MDMA and BDMA clocks
  dt-bindings: clk/ingenic: Add MDMA and BDMA clocks

* clk-mediatek:
  clk: mediatek: add mt7986 clock support
  clk: mediatek: add mt7986 clock IDs
  dt-bindings: clock: mediatek: document clk bindings for mediatek mt7986 SoC
  clk: mediatek: clk-gate: Use regmap_{set/clear}_bits helpers
  clk: mediatek: clk-gate: Shrink by adding clockgating bit check helper
Loading
Loading
Loading
Loading
+1 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ Required Properties:
	- "mediatek,mt7622-apmixedsys"
	- "mediatek,mt7623-apmixedsys", "mediatek,mt2701-apmixedsys"
	- "mediatek,mt7629-apmixedsys"
	- "mediatek,mt7986-apmixedsys"
	- "mediatek,mt8135-apmixedsys"
	- "mediatek,mt8167-apmixedsys", "syscon"
	- "mediatek,mt8173-apmixedsys"
+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ Required Properties:
	- "mediatek,mt7622-ethsys", "syscon"
	- "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
	- "mediatek,mt7629-ethsys", "syscon"
	- "mediatek,mt7986-ethsys", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ Required Properties:
	- "mediatek,mt7622-infracfg", "syscon"
	- "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
	- "mediatek,mt7629-infracfg", "syscon"
	- "mediatek,mt7986-infracfg", "syscon"
	- "mediatek,mt8135-infracfg", "syscon"
	- "mediatek,mt8167-infracfg", "syscon"
	- "mediatek,mt8173-infracfg", "syscon"
+2 −0
Original line number Diff line number Diff line
@@ -8,6 +8,8 @@ Required Properties:
- compatible: Should be:
	- "mediatek,mt7622-sgmiisys", "syscon"
	- "mediatek,mt7629-sgmiisys", "syscon"
	- "mediatek,mt7986-sgmiisys_0", "syscon"
	- "mediatek,mt7986-sgmiisys_1", "syscon"
- #clock-cells: Must be 1

The SGMIISYS controller uses the common clk binding from
+1 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ Required Properties:
	- "mediatek,mt7622-topckgen"
	- "mediatek,mt7623-topckgen", "mediatek,mt2701-topckgen"
	- "mediatek,mt7629-topckgen"
	- "mediatek,mt7986-topckgen", "syscon"
	- "mediatek,mt8135-topckgen"
	- "mediatek,mt8167-topckgen", "syscon"
	- "mediatek,mt8173-topckgen"
Loading