Commit 4ad7b396 authored by Moudy Ho's avatar Moudy Ho Committed by Mauro Carvalho Chehab
Browse files

media: dt-binding: mediatek: add bindings for MediaTek MDP3 components 



This patch adds DT binding documents for Media Data Path 3 (MDP3)
a unit in multimedia system combined with several components and
used for scaling and color format convert.

Signed-off-by: default avatarMoudy Ho <moudy.ho@mediatek.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: default avatarHans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@kernel.org>
parent 1c78f19c

Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek Read Direct Memory Access



maintainers:

  - Matthias Brugger <matthias.bgg@gmail.com>

  - Moudy Ho <moudy.ho@mediatek.com>



description: |

  MediaTek Read Direct Memory Access(RDMA) component used to do read DMA.

  It contains one line buffer to store the sufficient pixel data, and

  must be siblings to the central MMSYS_CONFIG node.

  For a description of the MMSYS_CONFIG binding, see

  Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml

  for details.



properties:

  compatible:

    items:

      - const: mediatek,mt8183-mdp3-rdma



  reg:

    maxItems: 1



  mediatek,gce-client-reg:

    $ref: '/schemas/types.yaml#/definitions/phandle-array'

    items:

      items:

        - description: phandle of GCE

        - description: GCE subsys id

        - description: register offset

        - description: register size

    description: The register of client driver can be configured by gce with

      4 arguments defined in this property. Each GCE subsys id is mapping to

      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.



  mediatek,gce-events:

    description:

      The event id which is mapping to the specific hardware event signal

      to gce. The event id is defined in the gce header

      include/dt-bindings/gce/<chip>-gce.h of each chips.

    $ref: /schemas/types.yaml#/definitions/uint32-array



  power-domains:

    maxItems: 1



  clocks:

    items:

      - description: RDMA clock

      - description: RSZ clock



  iommus:

    maxItems: 1



  mboxes:

    items:

      - description: used for 1st data pipe from RDMA

      - description: used for 2nd data pipe from RDMA



required:

  - compatible

  - reg

  - mediatek,gce-client-reg

  - mediatek,gce-events

  - power-domains

  - clocks

  - iommus

  - mboxes



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/mt8183-clk.h>

    #include <dt-bindings/gce/mt8183-gce.h>

    #include <dt-bindings/power/mt8183-power.h>

    #include <dt-bindings/memory/mt8183-larb-port.h>



    mdp3_rdma0: mdp3-rdma0@14001000 {

      compatible = "mediatek,mt8183-mdp3-rdma";

      reg = <0x14001000 0x1000>;

      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;

      mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,

                            <CMDQ_EVENT_MDP_RDMA0_EOF>;

      power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;

      clocks = <&mmsys CLK_MM_MDP_RDMA0>,

               <&mmsys CLK_MM_MDP_RSZ1>;

      iommus = <&iommu>;

      mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,

               <&gce 21 CMDQ_THR_PRIO_LOWEST>;

    };

Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek Resizer



maintainers:

  - Matthias Brugger <matthias.bgg@gmail.com>

  - Moudy Ho <moudy.ho@mediatek.com>



description: |

  One of Media Data Path 3 (MDP3) components used to do frame resizing.



properties:

  compatible:

    items:

      - enum:

          - mediatek,mt8183-mdp3-rsz



  reg:

    maxItems: 1



  mediatek,gce-client-reg:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      items:

        - description: phandle of GCE

        - description: GCE subsys id

        - description: register offset

        - description: register size

    description: The register of client driver can be configured by gce with

      4 arguments defined in this property. Each GCE subsys id is mapping to

      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.



  mediatek,gce-events:

    description:

      The event id which is mapping to the specific hardware event signal

      to gce. The event id is defined in the gce header

      include/dt-bindings/gce/<chip>-gce.h of each chips.

    $ref: /schemas/types.yaml#/definitions/uint32-array



  clocks:

    minItems: 1



required:

  - compatible

  - reg

  - mediatek,gce-client-reg

  - mediatek,gce-events

  - clocks



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/mt8183-clk.h>

    #include <dt-bindings/gce/mt8183-gce.h>



    mdp3_rsz0: mdp3-rsz0@14003000 {

      compatible = "mediatek,mt8183-mdp3-rsz";

      reg = <0x14003000 0x1000>;

      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;

      mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,

                            <CMDQ_EVENT_MDP_RSZ0_EOF>;

      clocks = <&mmsys CLK_MM_MDP_RSZ0>;

    };



    mdp3_rsz1: mdp3-rsz1@14004000 {

      compatible = "mediatek,mt8183-mdp3-rsz";

      reg = <0x14004000 0x1000>;

      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;

      mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,

                            <CMDQ_EVENT_MDP_RSZ1_EOF>;

      clocks = <&mmsys CLK_MM_MDP_RSZ1>;

    };

Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: MediaTek Write DMA with Rotation



maintainers:

  - Matthias Brugger <matthias.bgg@gmail.com>

  - Moudy Ho <moudy.ho@mediatek.com>



description: |

  One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.



properties:

  compatible:

    items:

      - enum:

          - mediatek,mt8183-mdp3-wrot



  reg:

    maxItems: 1



  mediatek,gce-client-reg:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      items:

        - description: phandle of GCE

        - description: GCE subsys id

        - description: register offset

        - description: register size

    description: The register of client driver can be configured by gce with

      4 arguments defined in this property. Each GCE subsys id is mapping to

      a client defined in the header include/dt-bindings/gce/<chip>-gce.h.



  mediatek,gce-events:

    description:

      The event id which is mapping to the specific hardware event signal

      to gce. The event id is defined in the gce header

      include/dt-bindings/gce/<chip>-gce.h of each chips.

    $ref: /schemas/types.yaml#/definitions/uint32-array



  power-domains:

    maxItems: 1



  clocks:

    minItems: 1



  iommus:

    maxItems: 1



required:

  - compatible

  - reg

  - mediatek,gce-client-reg

  - mediatek,gce-events

  - power-domains

  - clocks

  - iommus



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/mt8183-clk.h>

    #include <dt-bindings/gce/mt8183-gce.h>

    #include <dt-bindings/power/mt8183-power.h>

    #include <dt-bindings/memory/mt8183-larb-port.h>



    mdp3_wrot0: mdp3-wrot0@14005000 {

      compatible = "mediatek,mt8183-mdp3-wrot";

      reg = <0x14005000 0x1000>;

      mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;

      mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,

                            <CMDQ_EVENT_MDP_WROT0_EOF>;

      power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;

      clocks = <&mmsys CLK_MM_MDP_WROT0>;

      iommus = <&iommu>;

    };