Commit 4ab810a4 authored by Xiaoliang Yang's avatar Xiaoliang Yang Committed by David S. Miller
Browse files

net: mscc: ocelot: fix fields offset in SG_CONFIG_REG_3 



INIT_IPS and GATE_ENABLE fields have a wrong offset in SG_CONFIG_REG_3.
This register is used by stream gate control of PSFP, and it has not
been used before, because PSFP is not implemented in ocelot driver.

Signed-off-by: default avatarXiaoliang Yang <xiaoliang.yang_1@nxp.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent dba1e466

include/soc/mscc/ocelot_ana.h

+4 −4
Original line number Diff line number Diff line
@@ -252,10 +252,10 @@ 
#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_M                 GENMASK(18, 16)

#define ANA_SG_CONFIG_REG_3_LIST_LENGTH_X(x)              (((x) & GENMASK(18, 16)) >> 16)

#define ANA_SG_CONFIG_REG_3_GATE_ENABLE                   BIT(20)

#define ANA_SG_CONFIG_REG_3_INIT_IPS(x)                   (((x) << 24) & GENMASK(27, 24))

#define ANA_SG_CONFIG_REG_3_INIT_IPS_M                    GENMASK(27, 24)

#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x)                 (((x) & GENMASK(27, 24)) >> 24)

#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE               BIT(28)

#define ANA_SG_CONFIG_REG_3_INIT_IPS(x)                   (((x) << 21) & GENMASK(24, 21))

#define ANA_SG_CONFIG_REG_3_INIT_IPS_M                    GENMASK(24, 21)

#define ANA_SG_CONFIG_REG_3_INIT_IPS_X(x)                 (((x) & GENMASK(24, 21)) >> 21)

#define ANA_SG_CONFIG_REG_3_INIT_GATE_STATE               BIT(25)



#define ANA_SG_GCL_GS_CONFIG_RSZ                          0x4