Commit 4aa7e6e0 authored by YuBiao Wang's avatar YuBiao Wang Committed by Alex Deucher
Browse files

drm/amd/amdgpu: psp program IH_RB_CTRL on sienna_cichlid 



[Why]
IH_RB_CNTL is blocked by PSP so we need to ask psp to help config it.

[How]
Move psp ip block before ih, and use psp to program IH_RB_CNTL under sriov.

Reviewed-by: default avatarChen, Horace <Horace.Chen@amd.com>
Signed-off-by: default avatarYuBiao Wang <YuBiao.Wang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 49da4c2b

drivers/gpu/drm/amd/amdgpu/navi10_ih.c

+18 −2
Original line number Diff line number Diff line
@@ -151,7 +151,15 @@ static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev, 
	/* enable_intr field is only valid in ring0 */

	if (ih == &adev->irq.ih)

		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));



	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {

		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {

			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");

			return -ETIMEDOUT;

		}

	} else {

		WREG32(ih_regs->ih_rb_cntl, tmp);

	}



	if (enable) {

		ih->enabled = true;
@@ -261,7 +269,15 @@ static int navi10_ih_enable_ring(struct amdgpu_device *adev, 
		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);

		tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);

	}



	if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {

		if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {

			DRM_ERROR("PSP program IH_RB_CNTL failed!\n");

			return -ETIMEDOUT;

		}

	} else {

		WREG32(ih_regs->ih_rb_cntl, tmp);

	}



	if (ih == &adev->irq.ih) {

		/* set the ih ring 0 writeback address whether it's enabled or not */

drivers/gpu/drm/amd/amdgpu/nv.c

+9 −3
Original line number Diff line number Diff line
@@ -871,9 +871,15 @@ int nv_set_ip_blocks(struct amdgpu_device *adev) 
	case CHIP_SIENNA_CICHLID:

		amdgpu_device_ip_block_add(adev, &nv_common_ip_block);

		amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);

		if (!amdgpu_sriov_vf(adev)) {

			amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);

			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))

				amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);

		} else {

			if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))

				amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);

			amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);

		}

		if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&

		    is_support_sw_smu(adev))

			amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);