Commit 4a797d24 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
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drm/amd/display: Allow for plane-less resource reservation 



This change changes dc add plane logic to allow plane-less resource
reservation (pipe split).

If a free pipe_ctx (no plane_state attached) is the head pipe, and is
found with a bottom pipe attached, assign the plane to add on the bottom
pipe.

In addition, prepend dcn10 to dcn10-specific reset_back_end_for_pipe
and reset_hw_ctx_wrap

Signed-off-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 2750160b

drivers/gpu/drm/amd/display/dc/core/dc_resource.c

+3 −0
Original line number Diff line number Diff line
@@ -1214,6 +1214,9 @@ bool dc_add_plane_to_context( 
		free_pipe->clock_source = tail_pipe->clock_source;

		free_pipe->top_pipe = tail_pipe;

		tail_pipe->bottom_pipe = free_pipe;

	} else if (free_pipe->bottom_pipe && free_pipe->bottom_pipe->plane_state == NULL) {

		ASSERT(free_pipe->bottom_pipe->stream_res.opp != free_pipe->stream_res.opp);

		free_pipe->bottom_pipe->plane_state = plane_state;

	}



	/* assign new surfaces*/

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+5 −6
Original line number Diff line number Diff line
@@ -732,7 +732,7 @@ static enum dc_status dcn10_enable_stream_timing( 
	return DC_OK;

}



static void reset_back_end_for_pipe(

static void dcn10_reset_back_end_for_pipe(

		struct dc *dc,

		struct pipe_ctx *pipe_ctx,

		struct dc_state *context)
@@ -1173,7 +1173,7 @@ static void dcn10_init_hw(struct dc *dc) 
	memset(&dc->res_pool->clk_mgr->clks, 0, sizeof(dc->res_pool->clk_mgr->clks));

}



static void reset_hw_ctx_wrap(

static void dcn10_reset_hw_ctx_wrap(

		struct dc *dc,

		struct dc_state *context)

{
@@ -1195,10 +1195,9 @@ static void reset_hw_ctx_wrap( 
				pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {

			struct clock_source *old_clk = pipe_ctx_old->clock_source;



			reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);

			if (dc->hwss.enable_stream_gating) {

			dcn10_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);

			if (dc->hwss.enable_stream_gating)

				dc->hwss.enable_stream_gating(dc, pipe_ctx);

			}

			if (old_clk)

				old_clk->funcs->cs_power_down(old_clk);

		}
@@ -2944,7 +2943,7 @@ static const struct hw_sequencer_funcs dcn10_funcs = { 
	.pipe_control_lock = dcn10_pipe_control_lock,

	.prepare_bandwidth = dcn10_prepare_bandwidth,

	.optimize_bandwidth = dcn10_optimize_bandwidth,

	.reset_hw_ctx_wrap = reset_hw_ctx_wrap,

	.reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,

	.enable_stream_timing = dcn10_enable_stream_timing,

	.set_drr = set_drr,

	.get_position = get_position,